819 lines
40 KiB
Text
819 lines
40 KiB
Text
#################### This file is used by NXP NFC NCI HAL #####################
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###############################################################################
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# Application options
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# Logging Levels
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# NXPLOG_DEFAULT_LOGLEVEL 0x01
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# ANDROID_LOG_DEBUG 0x04
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# ANDROID_LOG_INFO 0x03
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# ANDROID_LOG_WARN 0x02
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# ANDROID_LOG_ERROR 0x01
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# ANDROID_LOG_SILENT 0x00
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NXPLOG_EXTNS_LOGLEVEL=0x04
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NXPLOG_NCIHAL_LOGLEVEL=0x04
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NXPLOG_NCIX_LOGLEVEL=0x04
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NXPLOG_NCIR_LOGLEVEL=0x04
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NXPLOG_FWDNLD_LOGLEVEL=0x04
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NXPLOG_TML_LOGLEVEL=0x04
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NFC_DEBUG_ENABLED=1
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###############################################################################
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# Nfc Device Node name
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NXP_NFC_DEV_NODE="/dev/nq-nci"
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#################################################################################
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#VEN Toggle Config
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#Disable = 0x00
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#Enable = 0x01
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ENABLE_VEN_TOGGLE=0x00
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###############################################################################
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# Extension for Mifare reader enable
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MIFARE_READER_ENABLE=0x01
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###############################################################################
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# Mifare Reader implementation
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# 0: General implementation
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# 1: Legacy implementation
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LEGACY_MIFARE_READER=0
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###############################################################################
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# System clock source selection configuration
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#define CLK_SRC_XTAL 1
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#define CLK_SRC_PLL 2
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NXP_SYS_CLK_SRC_SEL=0x02
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###############################################################################
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# System clock frequency selection configuration
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#define CLK_FREQ_13MHZ 1
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#define CLK_FREQ_19_2MHZ 2
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#define CLK_FREQ_24MHZ 3
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#define CLK_FREQ_26MHZ 4
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#define CLK_FREQ_38_4MHZ 5
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#define CLK_FREQ_52MHZ 6
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#define CLK_FREQ_32MHZ 7
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#define CLK_FREQ_48MHZ 8
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NXP_SYS_CLK_FREQ_SEL=0x02
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###############################################################################
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# The timeout value to be used for clock request acknowledgment
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# min value = 0x01 to max = 0x06
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#NXP_SYS_CLOCK_TO_CFG=0x06
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###############################################################################
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# The delay to try to start PLL/XTAL when using sys clock 256/fc units = ~18.8 us
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# min value = 0x01 to max = 0x1F
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#NXP_CLOCK_REQ_DELAY=0x16
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###############################################################################
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# NXP proprietary settings
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NXP_ACT_PROP_EXTN={2F, 02, 00}
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###############################################################################
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# NXP TVDD configurations settings
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# Allow NFCC to configure External TVDD, two configurations (1 and 2) supported,
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# out of them only one can be configured at a time.
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#NXP_EXT_TVDD_CFG=0x02
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###############################################################################
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#config1:SLALM, 3.3V for both RM and CM
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#NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01, 00, D0, 0C}
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###############################################################################
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#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
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#monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
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#NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, B2, 1E, 1F, 00, D0, 0C}
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#NXP_EXT_TVDD_CFG_2={20, 02, 24, 01, A0, 0E, 20, F0, 00, 1E, 15, 01, 01, 01, 00, 00, 00, 00, 00, A7, BE, FF, FF, 05, 00, 00, 00, 20, 20, 20, 20, 0A, 00, 00, 00, 0D, 0D, 0D, 08}
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#################################################################################
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# *** EVB_40x20 FW VERSION = 01.01.2A ***
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NXP_RF_CONF_BLK_1={
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20, 02, D9, 05,
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A0, 11, 07, 01, 0A, 32, 01, C8, 00, 00,
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A0, 0E, 20, F0, 00, 1E, 15, 01, 01, 01, 00, 00, 00, 00, 00, A7, BE, FF, FF, 05, 00, 00, 00, 24, 24, 24, 24, 0A, 00, 00, 00, 0D, 0D, 0D, 08,
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A0, A4, 85, 14, 00, 01, 00, 00, 00, 00, 00, 00, 01, 00, 03, 00, 05, 00, 07, 00, 08, 00, 0A, 00, 0C, 00, 0E, 00, 10, 00, 11, 00, 13, 00, 14, 00, 16, 00, 18, 00, 19, 00, 1A, 00, 1C, 00, 1D, 00, 1F, 00, 20, 00, 21, 00, 24, 00, 25, 00, 27, 00, 29, 00, 2A, 00, 2C, 00, 2D, 00, 2F, 00, 31, 00, 32, 00, 34, 00, 35, 00, 37, 00, 39, 00, 3A, 00, 3C, 00, 3D, 00, 3F, 00, 41, 00, 42, 00, 44, 00, 46, 00, 47, 00, 49, 00, 4A, 00, 4C, 00, 4E, 00, 4F, 00, 51, 00, 52, 00, 54, 00, 56, 00, 57, 00, 59, 00, 5A, 00, 5C, 00, 5E, 00, 5F, 00, 61, 00, 62, 00, 64, 00,
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A0, A5, 0D, 00, 00, 00, 00, 00, 00, FF, 03, 1F, 00, 00, 00, 00,
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A0, 6A, 10, B4, 00, B4, 00, B4, 00, B4, 00, 54, 01, 54, 01, 54, 01, 54, 01
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}
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NXP_RF_CONF_BLK_2={
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20, 02, CC, 01,
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A0, 34, C8, 23, 04, 3D, 01, 07, 0E, 80, 02, 00, 00, 80, 02, 00, 00, 80, 02, 00, 00, 80, 02, 00, 00, 80, 02, 00, 00, B6, 03, 00, 00, 14, 05, 00, 00, 27, 06, 00, 00, B8, 06, 00, 00, D0, 07, 00, 00, C4, 09, 00, 00, 80, 0C, 00, 00, AC, 0D, 00, 00, D8, 0E, 00, 00, D8, 0E, 00, 00, D8, 0E, 00, 00, D8, 0E, 00, 00, D8, 0E, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, 07, 0E, 80, 02, 00, 00, 80, 02, 00, 00, 80, 02, 00, 00, 80, 02, 00, 00, 80, 02, 00, 00, B6, 03, 00, 00, 14, 05, 00, 00, 27, 06, 00, 00, B8, 06, 00, 00, D0, 07, 00, 00, C4, 09, 00, 00, 80, 0C, 00, 00, AC, 0D, 00, 00, D8, 0E, 00, 00, D8, 0E, 00, 00, D8, 0E, 00, 00, D8, 0E, 00, 00, D8, 0E, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00
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}
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NXP_RF_CONF_BLK_3={
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20, 02, 66, 01,
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A1, 0A, 62, 07, 0E, 80, 02, 00, 00, 80, 02, 00, 00, 80, 02, 00, 00, 80, 02, 00, 00, 80, 02, 00, 00, B6, 03, 00, 00, 14, 05, 00, 00, 27, 06, 00, 00, B8, 06, 00, 00, D0, 07, 00, 00, C4, 09, 00, 00, 80, 0C, 00, 00, AC, 0D, 00, 00, D8, 0E, 00, 00, D8, 0E, 00, 00, D8, 0E, 00, 00, D8, 0E, 00, 00, D8, 0E, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00, A0, 0F, 00, 00
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}
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NXP_RF_CONF_BLK_4={
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20, 02, F1, 01,
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A0, A9, ED, 40, 24, FF, 41, 1E, FF, 42, 18, FF, 43, 13, FF, 44, 0E, FF, 45, 0A, FF, 46, 06, FF, 47, 03, FF, 07, 24, FF, 48, 00, FF, 09, 18, FF, 0A, 13, FF, 0B, 0E, FF, 0C, 0A, FF, 0D, 06, FF, 0E, 02, FF, 0F, 00, F5, 10, 00, DC, 11, 00, C6, 12, 00, B2, 13, 00, A0, 14, 00, 90, 15, 00, 81, 16, 00, 74, 17, 00, 68, 18, 00, 5D, 19, 00, 53, 1A, 00, 4A, 1B, 00, 42, 1C, 00, 3B, 1D, 00, 35, 1E, 00, 2F, 1F, 00, 2A, 20, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28, A1, 00, 28
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}
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NXP_RF_CONF_BLK_5={
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20, 02, 9E, 01,
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A0, 0B, 9A, 00, 00, 00, 14, 6A, 2A, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00
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}
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NXP_RF_CONF_BLK_6={
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20, 02, F1, 05,
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A0, AB, 82, 27, 1B, 5C, 06, 6F, 06, 86, 06, AF, 06, E4, 06, 1B, 07, 53, 07, 96, 07, DA, 07, 1F, 08, 74, 08, CA, 08, 22, 09, 91, 09, 01, 0A, 73, 0A, E6, 0A, 5B, 0B, F7, 0B, 95, 0C, 34, 0D, D4, 0D, 76, 0E, 38, 0F, FC, 0F, C0, 10, B6, 11, AE, 12, A6, 13, 9F, 14, 99, 15, E7, 16, 35, 18, 85, 19, D5, 1A, 25, 1C, 76, 1D, 70, 1F, 6A, 21, 66, 23, 62, 25, 5E, 27, 5A, 29, 01, 2C, A8, 2E, 4F, 31, F7, 33, 49, 37, 9C, 3A, EF, 3D, EC, 41, E9, 45, E7, 49, E5, 4D, 38, 53, 8C, 58, DF, 5D, 33, 63, 87, 68, 95, 6E, A4, 74, B2, 7A, B0, 82, B0, 8A,
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A0, AD, 0C, 00, 20, 00, 00, 00, 00, 00, 20, 00, 00, 00, 00,
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A0, A7, 0B, 00, 02, 77, 17, 14, 14, 1F, 0A, FF, 19, 05,
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A0, A8, 40, 00, 33, 33, 10, 00, 33, 23, 10, 00, 33, 24, 10, 4B, 11, 45, 10, CF, 22, 43, 10, CF, 22, 43, 10, CF, 22, 43, 10, CE, 22, 43, 10, CF, 22, 43, 10, CE, 22, 43, 10, 00, 33, 22, 10, C0, 22, 23, 10, 00, 33, 22, 10, C0, 22, 23, 10, 00, 33, 54, 10, 00, 33, 32, 10,
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A0, 98, 08, 3A, 30, 13, 80, 24, 3A, 35, 3A
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}
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NXP_RF_CONF_BLK_7={
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20, 02, FC, 0B,
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A0, 9E, 0C, 07, 30, 13, 96, 00, 2C, 01, 2B, C2, 01, 00, 00,
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A1, 2C, 5B, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 01, 01, 01, 20, 01, 03, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00,
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A1, 04, 05, 80, 24, 00, 00, 00,
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A1, 26, 08, 03, 03, 03, 03, 01, 01, 01, 01,
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A1, 27, 3B, 00, 00, 00, 68, 01, 00, 00, 00, 02, 00, 08, 9A, 00, F1, FF, 00, 00, 00, 00, 00, 00, B4, 00, 00, 00, 00, 00, 00, 00, E1, 00, 36, 00, A0, 00, 2C, 1A, 4D, 00, E0, 00, E0, 2E, 00, 00, 00, 00, 98, 3A, 00, FA, 00, FA, D0, 84, 42, 00, 23, 01,
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A1, 2E, 03, 82, 82, 22,
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A1, 4D, 10, 00, 40, 1F, 00, 00, 00, 00, 00, 94, 52, 4A, 01, 94, 52, 4A, 01,
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A0, 0D, 06, 10, C7, 00, 00, 00, 00,
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A0, 0D, 06, 11, C9, 30, 00, 00, 00,
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A0, 0D, 06, 12, 4C, 20, 0A, 00, 00,
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A0, 0D, 06, 12, 50, 94, 52, 4A, 29
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}
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NXP_RF_CONF_BLK_8={
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20, 02, FD, 1E,
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A0, 0D, 03, 24, 29, 08,
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A0, 0D, 03, 24, 30, 08,
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A0, 0D, 03, 25, 29, 03,
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A0, 0D, 03, 25, 30, 03,
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A0, 0D, 06, 40, 78, 00, 00, 00, 00,
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A0, 0D, 06, 42, 8B, 00, 04, 08, 00,
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A0, 0D, 06, 42, 87, 51, 02, 00, E0,
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A0, 0D, 06, 42, 89, 7F, 07, 1D, 01,
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A0, 0D, 06, 42, 88, AF, E0, 8B, 48,
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A0, 0D, 06, 42, 44, 00, 34, 26, 00,
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A0, 0D, 06, 42, 40, 08, 77, 7F, 3A,
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A0, 0D, 06, 42, 79, 55, 21, 08, 4C,
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A0, 0D, 06, 42, 4A, 8E, 61, B0, 01,
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A0, 0D, 06, 42, 49, 7D, 26, 0B, 00,
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A0, 0D, 06, 51, 40, 8A, 88, 33, 3A,
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A0, 0D, 03, 43, 7C, 40,
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A0, 0D, 06, 43, 8B, 4C, 04, F8, 10,
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A0, 0D, 06, 43, 88, 54, E1, 86, 88,
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A0, 0D, 06, 43, 44, 00, 34, 12, 00,
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A0, 0D, 06, 43, 40, 88, 88, B3, 3C,
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A0, 0D, 06, 43, 79, 55, 21, 08, 4C,
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A0, 0D, 06, 43, 4A, 8E, 61, B0, 01,
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A0, 0D, 06, 43, 49, 7D, 26, 0B, 00,
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A0, 0D, 03, 44, 7C, 40,
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A0, 0D, 06, 44, 8B, 28, 04, F8, 14,
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A0, 0D, 06, 44, 88, 4C, E5, 04, 88,
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A0, 0D, 06, 44, 44, 00, 34, 12, 00,
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A0, 0D, 06, 44, 40, 8C, 88, B3, 3C,
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A0, 0D, 06, 44, 79, 55, 21, 08, 4C,
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A0, 0D, 06, 44, 4A, 8E, 61, B0, 01
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}
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NXP_RF_CONF_BLK_9={
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20, 02, F7, 1C,
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A0, 0D, 06, 44, 49, 7D, 26, 0B, 00,
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A0, 0D, 03, 45, 7C, 40,
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A0, 0D, 06, 45, 8B, 09, 04, F8, 28,
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A0, 0D, 06, 45, 88, 0C, E5, 02, 40,
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A0, 0D, 06, 45, 44, 00, 34, 12, 00,
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A0, 0D, 06, 45, 40, 90, 88, B3, 3C,
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A0, 0D, 06, 45, 79, 55, 21, 08, 4C,
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A0, 0D, 06, 45, 4A, 8E, 61, B0, 01,
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A0, 0D, 06, 45, 49, 7D, 26, 0B, 00,
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A0, 0D, 06, 45, 45, 38, B2, 88, A6,
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A0, 0D, 06, 46, 45, 38, 92, 88, A6,
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A0, 0D, 03, 46, 7C, 40,
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A0, 0D, 06, 47, 8B, 48, 04, 38, 3E,
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A0, 0D, 06, 47, 87, 01, 03, 00, E0,
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A0, 0D, 06, 47, 88, 54, E2, 08, 95,
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A0, 0D, 06, 47, 40, 86, 88, B3, 3C,
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A0, 0D, 06, 47, 44, 00, 34, 12, 00,
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A0, 0D, 06, 47, 4A, B3, CD, 66, 06,
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A0, 0D, 06, 47, 49, 00, 00, 00, 00,
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A0, 0D, 06, 47, 79, 55, 21, 08, 4C,
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A0, 0D, 06, 48, 8B, 48, 04, 38, 10,
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A0, 0D, 06, 48, 88, 4C, E2, 86, 94,
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A0, 0D, 06, 48, 40, 88, 88, B3, 3C,
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A0, 0D, 06, 48, 44, 00, 34, 12, 00,
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A0, 0D, 06, 48, 4A, B3, CD, 66, 06,
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A0, 0D, 06, 48, 49, 00, 00, 00, 00,
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A0, 0D, 06, 48, 79, 55, 21, 08, 4C,
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A0, 0D, 06, 49, 8B, 48, 04, 38, 20
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}
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NXP_RF_CONF_BLK_10={
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20, 02, F7, 1C,
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A0, 0D, 06, 49, 88, 54, E6, 04, 94,
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A0, 0D, 06, 49, 40, 8C, 88, B3, 3C,
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A0, 0D, 06, 49, 44, 00, 34, 12, 00,
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A0, 0D, 06, 49, 4A, B3, CD, 66, 06,
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A0, 0D, 06, 49, 49, 00, 00, 00, 00,
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A0, 0D, 06, 49, 79, 55, 21, 08, 4C,
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A0, 0D, 06, 4A, 8B, 09, 04, 38, 0A,
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A0, 0D, 06, 4A, 88, 0C, E6, 02, 5C,
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A0, 0D, 06, 4A, 40, 90, 88, B3, 3C,
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A0, 0D, 06, 4A, 44, 00, 34, 12, 00,
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A0, 0D, 06, 4A, 4A, B3, CD, 66, 06,
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A0, 0D, 06, 4A, 49, 00, 00, 00, 00,
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A0, 0D, 06, 4A, 79, 55, 21, 08, 4C,
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A0, 0D, 03, 4C, 7C, 50,
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A0, 0D, 06, 4C, 8B, 28, 04, 78, 14,
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A0, 0D, 06, 4C, 88, 04, E1, 80, 01,
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A0, 0D, 06, 4C, 44, 00, 34, 12, 00,
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A0, 0D, 06, 4C, 4A, 8E, 61, B0, 01,
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A0, 0D, 06, 4C, 49, 00, 00, 00, 00,
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A0, 0D, 06, 4C, 79, 55, 21, 08, 4C,
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A0, 0D, 06, 4C, 40, 87, 88, B3, 3C,
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A0, 0D, 03, 4D, 7C, 40,
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A0, 0D, 06, 4D, 87, 03, 03, 00, C0,
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A0, 0D, 06, 4D, 88, 4C, E5, 82, 48,
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A0, 0D, 06, 4D, 44, 00, 34, 12, 00,
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A0, 0D, 06, 4D, 4A, 8E, 61, B0, 01,
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A0, 0D, 06, 4D, 49, 00, 00, 00, 00,
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A0, 0D, 06, 4D, 79, 55, 21, 08, 4C
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}
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NXP_RF_CONF_BLK_11={
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20, 02, FD, 1C,
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A0, 0D, 06, 4D, 40, 8A, 88, B3, 3C,
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A0, 0D, 06, 4E, 4A, BA, E6, F1, 06,
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A0, 0D, 06, 4E, 49, DD, 95, 0A, 00,
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|
A0, 0D, 06, 4E, 5C, EF, 7F, 00, 00,
|
|
A0, 0D, 06, 4E, 78, 00, 00, C0, 00,
|
|
A0, 0D, 06, 4F, 88, F7, E0, 16, 89,
|
|
A0, 0D, 06, 4F, 8B, 00, 14, 08, 00,
|
|
A0, 0D, 06, 4F, 89, 7F, 07, 15, 02,
|
|
A0, 0D, 06, 4F, 44, 00, 34, E6, 00,
|
|
A0, 0D, 06, 4F, 40, 84, 88, B3, 3C,
|
|
A0, 0D, 06, 4F, 79, 55, 21, 88, 4C,
|
|
A0, 0D, 06, 50, 88, 9F, E0, 2B, 41,
|
|
A0, 0D, 06, 50, 8B, 00, 14, 08, 00,
|
|
A0, 0D, 06, 50, 89, 7F, 07, 15, 02,
|
|
A0, 0D, 06, 50, 44, 00, 34, E6, 00,
|
|
A0, 0D, 06, 50, 40, 84, 88, B3, 3C,
|
|
A0, 0D, 06, 50, 79, 55, 21, 88, 4C,
|
|
A0, 0D, 06, 52, 88, 9F, E8, A2, 40,
|
|
A0, 0D, 06, 52, 8B, 00, 14, 08, 00,
|
|
A0, 0D, 06, 52, 89, 7F, 07, 15, 02,
|
|
A0, 0D, 06, 52, 44, 00, 34, E6, 00,
|
|
A0, 0D, 06, 52, 40, 84, 88, B3, 3C,
|
|
A0, 0D, 06, 52, 79, 55, 21, 88, 4C,
|
|
A0, 0D, 06, 53, 88, 9F, E8, 2C, 40,
|
|
A0, 0D, 06, 53, 89, 7F, 07, 15, 02,
|
|
A0, 0D, 06, 53, 44, 00, 34, E6, 00,
|
|
A0, 0D, 06, 53, 40, 84, 88, B3, 3C,
|
|
A0, 0D, 06, 53, 79, 55, 21, 88, 4C
|
|
}
|
|
|
|
NXP_RF_CONF_BLK_12={
|
|
20, 02, FD, 1C,
|
|
A0, 0D, 06, 60, 50, 94, 52, 4A, 29,
|
|
A0, 0D, 06, 80, 83, 1F, 06, 00, 00,
|
|
A0, 0D, 06, 80, 82, 25, 0A, 00, 20,
|
|
A0, 0D, 06, 80, 80, 10, 42, 24, 00,
|
|
A0, 0D, 06, 80, 7E, 28, 02, 00, 00,
|
|
A0, 0D, 06, 80, 8F, 80, 42, D6, 0A,
|
|
A0, 0D, 06, 80, 90, 00, A2, 52, 2A,
|
|
A0, 0D, 06, 80, 49, ED, 16, 0B, 00,
|
|
A0, 0D, 06, 82, 82, 25, 0A, 00, 20,
|
|
A0, 0D, 06, 82, 49, ED, 16, 0B, 00,
|
|
A0, 0D, 06, 83, 80, 3A, 01, 20, 00,
|
|
A0, 0D, 06, 83, 49, ED, 16, 0B, 00,
|
|
A0, 0D, 06, 84, 7F, 1E, 01, 20, 00,
|
|
A0, 0D, 06, 85, 7F, 0E, 01, 20, 00,
|
|
A0, 0D, 06, 85, 7D, B3, 22, F6, BF,
|
|
A0, 0D, 06, 87, 83, 1F, 06, 00, 00,
|
|
A0, 0D, 06, 87, 49, ED, 16, 0B, 00,
|
|
A0, 0D, 06, 88, 83, 3C, 0E, 00, 00,
|
|
A0, 0D, 06, 88, 49, ED, 16, 0B, 00,
|
|
A0, 0D, 06, 89, 80, 1E, 01, 20, 00,
|
|
A0, 0D, 06, 89, 49, ED, 16, 0B, 00,
|
|
A0, 0D, 06, 8A, 7F, 0C, 01, 20, 00,
|
|
A0, 0D, 06, 8C, 80, 10, 42, 24, 00,
|
|
A0, 0D, 06, 8C, 49, ED, 16, 0B, 00,
|
|
A0, 0D, 06, 8D, 49, ED, 16, 0B, 00,
|
|
A0, 0D, 06, 90, 38, D9, 39, A9, 80,
|
|
A0, 0D, 06, 91, AC, 94, 52, 4A, 29,
|
|
A0, 0D, 06, 91, AE, 94, 52, 4A, 29
|
|
}
|
|
|
|
NXP_RF_CONF_BLK_13={
|
|
20, 02, 65, 03,
|
|
A0, AF, 09, 10, 46, 00, 24, 10, 46, 00, 24, 12,
|
|
A0, 92, 28, 48, 00, 24, 00, FC, 81, 0F, 00, 22, 80, 0F, 00, 14, 00, 20, 60, EA, 01, 43, 18, 32, 16, 78, 30, 0D, 00, 03, 45, EA, 05, 01, 04, 68, 02, 3F, 92, 04, 00, 0C, 13,
|
|
A0, 68, 2A, 06, 40, 60, 03, 19, 14, 00, 00, 00, 82, 24, 00, 00, 0A, 00, 0A, 00, 01, 00, 01, A0, 00, A0, 00, 03, FA, 00, 00, 00, 4C, 00, 14, 00, 7D, 00, 0A, 7F, 00, 00, 01, 00, 03
|
|
}
|
|
|
|
NXP_RF_CONF_MAX_NUM=13
|
|
|
|
###############################################################################
|
|
# Core configuration rf field filter settings to enable set to 01 to disable set
|
|
# to 00 last bit
|
|
#NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 00 }
|
|
|
|
###############################################################################
|
|
# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set
|
|
# to 0x00
|
|
#NXP_I2C_FRAGMENTATION_ENABLED=0x00
|
|
|
|
###############################################################################
|
|
#set autonomous mode
|
|
# disable autonomous 0x00
|
|
# enable autonomous 0x01
|
|
NXP_AUTONOMOUS_ENABLE=0x00
|
|
###############################################################################
|
|
#set Guard Timer
|
|
# Gurad Timer range to 0x0F-0xFF(i.e.15-255 seconds)
|
|
NXP_GUARD_TIMER_VALUE=0x0F
|
|
###############################################################################
|
|
#Enable SWP full power mode when phone is power off
|
|
#NXP_SWP_FULL_PWR_ON=0x00
|
|
|
|
################################################################################
|
|
#This is used to configure UICC2 at boot time.
|
|
# UICC2 0x03
|
|
NXP_DEFAULT_UICC2_SELECT=0x03
|
|
###############################################################################
|
|
# CE when Screen state is locked
|
|
# This setting is for DEFAULT_AID_ROUTE,
|
|
# DEFAULT_DESFIRE_ROUTE and DEFAULT_MIFARE_CLT_ROUTE
|
|
# Disable 0x00
|
|
# Enable 0x01
|
|
NXP_CE_ROUTE_STRICT_DISABLE=0x01
|
|
|
|
###############################################################################
|
|
#SCR Read Tag Operation Timeout in secs
|
|
NXP_SWP_RD_TAG_OP_TIMEOUT=20
|
|
|
|
###############################################################################
|
|
#Set the default AID route Location :
|
|
#This settings will be used when application does not set this parameter
|
|
# host 0x00
|
|
# eSE 0x01
|
|
# UICC 0x02
|
|
# UICC2 0x03
|
|
DEFAULT_AID_ROUTE=0x01
|
|
|
|
###############################################################################
|
|
#Set the ISODEP (Mifare Desfire) route Location :
|
|
#This settings will be used when application does not set this parameter
|
|
# host 0x00
|
|
# eSE 0x01
|
|
# UICC 0x02
|
|
# UICC2 0x03
|
|
DEFAULT_ISODEP_ROUTE=0x01
|
|
|
|
###############################################################################
|
|
#Set the Mifare CLT route Location :
|
|
#This settings will be used when application does not set this parameter
|
|
# host 0x00
|
|
# eSE 0x01
|
|
# UICC 0x02
|
|
# UICC2 0x03
|
|
DEFAULT_MIFARE_CLT_ROUTE=0x01
|
|
|
|
###############################################################################
|
|
#Set the Felica CLT route Location :
|
|
#This settings will be used when application does not set this parameter
|
|
# eSE 0x01
|
|
# UICC 0x02
|
|
# UICC2 0x03
|
|
DEFAULT_FELICA_CLT_ROUTE=0x01
|
|
|
|
###############################################################################
|
|
#Set the default AID Power state :
|
|
#This settings will be used when application does not set this parameter
|
|
# bit pos 0 = Switch On
|
|
# bit pos 1 = Switch Off
|
|
# bit pos 2 = Battery Off
|
|
# bit pos 3 = Screen off unlock
|
|
# bit pos 4 = Screen On lock
|
|
# bit pos 5 = Screen Off lock
|
|
DEFAULT_AID_PWR_STATE=0x39
|
|
###############################################################################
|
|
#Set the Mifare Desfire Power state :
|
|
#This settings will be used when application does not set this parameter
|
|
# bit pos 0 = Switch On
|
|
# bit pos 1 = Switch Off
|
|
# bit pos 2 = Battery Off
|
|
# bit pos 3 = Screen off unlock
|
|
# bit pos 4 = Screen On lock
|
|
# bit pos 5 = Screen Off lock
|
|
DEFAULT_DESFIRE_PWR_STATE=0x3B
|
|
|
|
###############################################################################
|
|
#Set the Mifare CLT Power state :
|
|
#This settings will be used when application does not set this parameter
|
|
# bit pos 0 = Switch On
|
|
# bit pos 1 = Switch Off
|
|
# bit pos 2 = Battery Off
|
|
# bit pos 3 = Screen off unlock
|
|
# bit pos 4 = Screen On lock
|
|
# bit pos 5 = Screen Off lock
|
|
DEFAULT_MIFARE_CLT_PWR_STATE=0x3B
|
|
|
|
###############################################################################
|
|
#Set the Felica CLT Power state :
|
|
#This settings will be used when application does not set this parameter
|
|
# bit pos 0 = Switch On
|
|
# bit pos 1 = Switch Off
|
|
# bit pos 2 = Battery Off
|
|
# bit pos 3 = Screen off unlock
|
|
# bit pos 4 = Screen On lock
|
|
# bit pos 5 = Screen Off lock
|
|
DEFAULT_FELICA_CLT_PWR_STATE=0x3B
|
|
|
|
###############################################################################
|
|
#Set the T4TNfcee AID Power state :
|
|
#This settings will be used when application does not set this parameter
|
|
# bit pos 0 = Switch On
|
|
# bit pos 1 = Switch Off
|
|
# bit pos 2 = Battery Off
|
|
# bit pos 3 = Screen off unlock
|
|
# bit pos 4 = Screen On lock
|
|
# bit pos 5 = Screen Off lock
|
|
DEFAULT_T4TNFCEE_AID_POWER_STATE=0x3B
|
|
|
|
###############################################################################
|
|
#Set the default Felica T3T System Code OffHost route Location :
|
|
#This settings will be used when application does not set this parameter
|
|
# host 0x00
|
|
# eSE 0x01
|
|
# UICC 0x02
|
|
# UICC2 0x03
|
|
DEFAULT_SYS_CODE_ROUTE=0x00
|
|
###############################################################################
|
|
# AID Matching platform options
|
|
# AID_MATCHING_L 0x01
|
|
# AID_MATCHING_K 0x02
|
|
#AID_MATCHING_PLATFORM=0x01
|
|
|
|
###############################################################################
|
|
# P61 interface options
|
|
# SPI 0x02
|
|
NXP_P61_LS_DEFAULT_INTERFACE=0x00
|
|
|
|
###############################################################################
|
|
#CHINA_TIANJIN_RF_SETTING
|
|
#Enable 0x01
|
|
#Disable 0x00
|
|
#NXP_CHINA_TIANJIN_RF_ENABLED=0x01
|
|
|
|
###############################################################################
|
|
#SWP_SWITCH_TIMEOUT_SETTING
|
|
# Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60].
|
|
# Timeout in milliseconds, for example
|
|
# No Timeout 0x00
|
|
# 10 millisecond timeout 0x0A
|
|
#NXP_SWP_SWITCH_TIMEOUT=0x0A
|
|
|
|
###############################################################################
|
|
# Flashing Options Configurations
|
|
# FLASH_UPPER_VERSION 0x01
|
|
# FLASH_DIFFERENT_VERSION 0x02
|
|
# FLASH_ALWAYS 0x03
|
|
NXP_FLASH_CONFIG=0x02
|
|
|
|
###############################################################################
|
|
# P61 interface options for JCOP Download
|
|
# SPI 0x02
|
|
NXP_P61_JCOP_DEFAULT_INTERFACE=0x00
|
|
|
|
###############################################################################
|
|
# Option to perform LS update every boot
|
|
# Enable 0x01
|
|
# Disable 0x00
|
|
NXP_LS_FORCE_UPDATE_REQUIRED=0x00
|
|
|
|
###############################################################################
|
|
# Option to perform JCOP update every boot
|
|
# Enable 0x01
|
|
# Disable 0x00
|
|
NXP_JCOP_FORCE_UPDATE_REQUIRED=0x00
|
|
|
|
###############################################################################
|
|
# Bail out mode
|
|
# If set to 1, NFCC is using bail out mode for either Type A or Type B poll.
|
|
# Set this parameter value to 1 if Android Beam is enabled, else set to 0.
|
|
NFA_POLL_BAIL_OUT_MODE=0x00
|
|
|
|
###############################################################################
|
|
# White list of Hosts
|
|
# This values will be the Hosts(NFCEEs) in the HCI Network.
|
|
DEVICE_HOST_WHITE_LIST={C0, 80}
|
|
|
|
###############################################################################
|
|
# Choose the presence-check algorithm for type-4 tag. If not defined, the default value is 1.
|
|
# 0 NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm
|
|
# 1 NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block
|
|
# 2 NFA_RW_PRES_CHK_ISO_DEP_NAK; Type - 4 tag protocol iso-dep nak presence check
|
|
# command is sent waiting for rsp and ntf.
|
|
PRESENCE_CHECK_ALGORITHM=2
|
|
###############################################################################
|
|
# Options to Fallback to alternative route
|
|
# DH 0x01
|
|
# ESE 0x02
|
|
NXP_CHECK_DEFAULT_PROTO_SE_ID=0x01
|
|
###############################################################################
|
|
# Vendor Specific Proprietary Protocol & Discovery Configuration
|
|
# Set to 0xFF if unsupported
|
|
# byte[0] NCI_PROTOCOL_18092_ACTIVE
|
|
# byte[1] NCI_PROTOCOL_B_PRIME
|
|
# byte[2] NCI_PROTOCOL_DUAL
|
|
# byte[3] NCI_PROTOCOL_15693
|
|
# byte[4] NCI_PROTOCOL_KOVIO
|
|
# byte[5] NCI_PROTOCOL_MIFARE
|
|
# byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO
|
|
# byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME
|
|
# byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME
|
|
NFA_PROPRIETARY_CFG={05, FF, FF, 06, 81, 80, FF, FF, FF}
|
|
|
|
###############################################################################
|
|
#NXP_CN_TRANSIT_BLK_NUM_CHECK_ENABLE
|
|
#Enable/Disable block number checks for china transit use case
|
|
#Enable 0x01
|
|
#Disable 0x00
|
|
#NXP_CN_TRANSIT_BLK_NUM_CHECK_ENABLE=0x01
|
|
|
|
################################################################################
|
|
#This flags will enable different modes of Lx Debug based on bits of the Byte0
|
|
#Byte 0:
|
|
# |_________Bit Mask_______| Debug Mode
|
|
# b7|b6|b5|b4|b3|b2|b1|b0|
|
|
# | |x | | | | | | Modulation Detected Notification
|
|
# | | |X | | | | | Enable L1 Events (ISO14443-4, ISO18092)
|
|
# | | | |X | | | | Enable L2 Reader Events(ROW specific)
|
|
# | | | | |X | | | Enable Felica SystemCode
|
|
# | | | | | |X | | Enable Felica RF (all Felica CM events)
|
|
# | | | | | | |X | Enable L2 Events CE (ISO14443-3, RF Field ON/OFF)
|
|
#Byte 1:
|
|
# |_________Bit Mask_______| Debug Mode
|
|
# b7|b6|b5|b4|b3|b2|b1|b0|
|
|
# | |x | | | | | | Enable L2 events during RF activation ISO 14443-3
|
|
# | | | | | | | |
|
|
# | | | | | | | |
|
|
# | | | | | | | |
|
|
# | | | | | | | |
|
|
# | | | | | | | |
|
|
# Byte1 Byte0
|
|
# \__ __/
|
|
# e.g. NXP_CORE_PROP_SYSTEM_DEBUG=0x0031 ==> Modulation detected, L1, L2 CE
|
|
NXP_CORE_PROP_SYSTEM_DEBUG=0x0000
|
|
|
|
###############################################################################
|
|
#Enable NXP NCI runtime parser library
|
|
#Enable 0x01
|
|
#Disable 0x00
|
|
NXP_NCI_PARSER_LIBRARY=0x00
|
|
|
|
###############################################################################
|
|
# Timeout value in milliseconds for JCOP OS download to complete
|
|
OS_DOWNLOAD_TIMEOUT_VALUE=60000
|
|
|
|
###############################################################################
|
|
# Forcing HOST to listen for a selected protocol
|
|
# 0x00 : Disable Host Listen
|
|
# 0x01 : Enable Host to Listen (A) for ISO-DEP tech A
|
|
# 0x02 : Enable Host to Listen (B) for ISO-DEP tech B
|
|
# 0x04 : Enable Host to Listen (F) for T3T Tag Type Protocol tech F
|
|
# 0x07 : Enable Host to Listen (ABF)for ISO-DEP tech AB & T3T Tag Type Protocol tech F
|
|
HOST_LISTEN_TECH_MASK=0x07
|
|
|
|
###############################################################################
|
|
# Enable forward functionality
|
|
# Disable 0x00
|
|
# Enable 0x01 //Any positive value as per below bit configuration
|
|
# HOST power states when type A/B only UICC present
|
|
# bit pos 0 = Switch On
|
|
# bit pos 1 = Switch Off
|
|
# bit pos 2 = Battery Off
|
|
# bit pos 3 = Screen off unlock
|
|
# bit pos 4 = Screen On lock
|
|
# bit pos 5 = Screen Off lock
|
|
FORWARD_FUNCTIONALITY_ENABLE=0x01
|
|
|
|
###############################################################################
|
|
# Configure the NFC Extras to open and use a static pipe. If the value is
|
|
# not set or set to 0, then the default is use a dynamic pipe based on a
|
|
# destination gate (see NFA_HCI_DEFAULT_DEST_GATE). Note there is a value
|
|
# for each EE (ESE/SIM1/SIM2)
|
|
OFF_HOST_ESE_PIPE_ID=0x16
|
|
OFF_HOST_SIM_PIPE_ID=0x0A
|
|
OFF_HOST_SIM2_PIPE_ID=0x23
|
|
|
|
###############################################################################
|
|
#Set the Felica T3T System Code Power state :
|
|
#This settings will be used when application does not set this parameter
|
|
#Update Power state as per NCI2.0
|
|
DEFAULT_SYS_CODE_PWR_STATE=0x00
|
|
###############################################################################
|
|
#Default Secure Element route id
|
|
DEFAULT_OFFHOST_ROUTE=0x01
|
|
|
|
###############################################################################
|
|
#Maximum SMB transceive wait for response
|
|
NXP_SMB_TRANSCEIVE_TIMEOUT=2000
|
|
###############################################################################
|
|
# Firmware file type
|
|
#.so file 0x01
|
|
#.bin file 0x02
|
|
NXP_FW_TYPE=0x01
|
|
############################################################################
|
|
# Extended APDU length for ISO_DEP
|
|
ISO_DEP_MAX_TRANSCEIVE=0xFEFF
|
|
#########################################################################
|
|
# Support for Amendment I SEMS specification
|
|
# Support SEMS Amendment I 0x01
|
|
# Support NXP LS client 0x00
|
|
NXP_GP_AMD_I_SEMS_SUPPORTED=0x01
|
|
###############################################################################
|
|
#All eSE terminals shall be match with the /vendor/etc/vintf/manifest.xml file
|
|
#under android.hardware.secure_element.
|
|
# The terminal name shall start from 1
|
|
# Assign terminal number to each interface based on system config
|
|
NXP_SPI_SE_TERMINAL_NUM="eSE1"
|
|
###############################################################################
|
|
# Assign terminal number to each interface based on system config
|
|
#NXP_VISO_SE_TERMINAL_NUM="eSE3"
|
|
###############################################################################
|
|
# Assign terminal number to each interface based on system config
|
|
NXP_NFC_SE_TERMINAL_NUM="eSE2"
|
|
###############################################################################
|
|
#For static or dynamic dual UICC feature support
|
|
#Enable static dual uicc feature by setting value 0x00
|
|
#Enable dynamic dual uicc feature by setting value 0x01
|
|
NXP_DUAL_UICC_ENABLE=0x01
|
|
###############################################################################
|
|
# Time to wait by DH when NFCC will report eSE Cold Temp Error.
|
|
# The value is as per the UM and in seconds
|
|
NXP_SE_COLD_TEMP_ERROR_DELAY=0x05
|
|
|
|
###############################################################################
|
|
# Set configuration optimization decision setting
|
|
# Enable = 0x01
|
|
# Disable = 0x00
|
|
NXP_SET_CONFIG_ALWAYS=0x01
|
|
|
|
###############################################################################
|
|
#OffHost ESE route location for MultiSE
|
|
#ESE = 01
|
|
OFFHOST_ROUTE_ESE={01}
|
|
|
|
###############################################################################
|
|
#OffHost UICC route location for MultiSE
|
|
#UICC1 = 02
|
|
#UICC2 = 03
|
|
OFFHOST_ROUTE_UICC={02:03}
|
|
|
|
###############################################################################
|
|
#T4T NFCEE ENABLE
|
|
#bit pos 0 = T4T NFCEE Enable
|
|
#bit pos 6 = T4T NFCEE Contactless write enable
|
|
#bit pos 7 = Proprietary file enable
|
|
NXP_T4T_NFCEE_ENABLE=0x01
|
|
|
|
###############################################################################
|
|
#WLC mode
|
|
#0x00 = if WLC Application running in MW (non-autonomous mode)
|
|
#0x01 = if WLC Application running in FW (autonomous mode)
|
|
NXP_WLC_MODE=0x01
|
|
|
|
###############################################################################
|
|
#CORE_SET_CONF_CMD to reset Prop Emvco Flag
|
|
NXP_PROP_RESET_EMVCO_CMD={20, 02, 05, 01, A0, 44, 01, 00}
|
|
|
|
###############################################################################
|
|
#Guard time in ms for the mPOS/SCR module to process the reader start/stop req
|
|
NXP_RDR_REQ_GUARD_TIME=0
|
|
|
|
###############################################################################
|
|
#MW workaround to enable LPCD when EMVCO polling mode starts and disable
|
|
#while switching back to NFC Forum mode
|
|
# 0 --> Disable MW workaround
|
|
# 1 --> Enable MW workaround
|
|
# 2 --> Use this option only for FW versions below 1.10.52
|
|
NXP_RDR_DISABLE_ENABLE_LPCD=1
|
|
|
|
###############################################################################
|
|
# Firmware patch format, Only 1 and 5 should be set
|
|
# 0 -> NFC Default
|
|
# 1 -> EMVCO Default
|
|
# 3 -> EMVCO Polling, DISC_IDLE = POWER_OFF, DISC DEACTIVATE = Removal process
|
|
# 5 -> EMVCO Cert Polling, DISC_IDLE = Removal process , DISC DEACTIVATE = POWER_OFF
|
|
# 7 -> EMVCO Polling, DISC_IDLE = POWER_OFF, DISC DEACTIVATE = POWER_OFF
|
|
NFA_CONFIG_FORMAT=1
|
|
|
|
################################################################################
|
|
# Enable disconnect tag in screen off
|
|
# Disable 0x00
|
|
# Enable 0x01
|
|
NXP_DISCONNECT_TAG_IN_SCRN_OFF=0x01
|
|
|
|
#################################################################################
|
|
# Core configuration extensions
|
|
# It includes
|
|
# Wired mode settings A0ED, A0EE
|
|
# Tag Detector A040, A041, A043
|
|
# Low Power mode A007
|
|
# Clock settings A002, A003
|
|
# PbF settings A008
|
|
# Clock timeout settings A004
|
|
# eSE (SVDD) PWR REQ settings A0F2
|
|
# Window size A0D8
|
|
# DWP Speed A0D5
|
|
# How eSE connected to PN553 A012
|
|
# UICC2 bit rate A0D1
|
|
# UICC1 interface A0EC
|
|
# UICC2 interface A0D4
|
|
# eSE interface A0ED
|
|
# DWP intf behavior config, SVDD Load activated by default if set to 0x31 A037
|
|
# Low power tag detection LPTD for power reduction A068
|
|
NXP_CORE_CONF_EXTN={20, 02, 11, 04,
|
|
A0, EC, 01, 01,
|
|
A0, ED, 01, 01,
|
|
A0, D4, 01, 00,
|
|
A0, 0A, 01, 0A
|
|
}
|
|
# A0, F2, 01, 01,
|
|
# A0, 40, 01, 01,
|
|
# A0, 41, 01, 02,
|
|
# A0, 43, 01, 04,
|
|
# A0, 02, 01, 01,
|
|
# A0, 03, 01, 11,
|
|
# A0, 07, 01, 03,
|
|
# A0, 08, 01, 01
|
|
# }
|
|
|
|
###############################################################################
|
|
# Core configuration settings
|
|
# Below params are not recommended to add in CONF block.
|
|
# LA_BIT_FRAME_SDD(0x30)
|
|
# LA_PLATFORM_CONFIG(0x31)
|
|
# LA_SEL_INFO(0x32)
|
|
# LB_SENSB_INFO(0x38)
|
|
# LF_PROTOCOL(0x50)
|
|
# NFCC_CONFIG_CONTROL(0x85)
|
|
|
|
NXP_CORE_CONF={ 20, 02, 37, 11,
|
|
28, 01, 00,
|
|
21, 01, 00,
|
|
30, 01, 08,
|
|
31, 01, 03,
|
|
32, 01, 60,
|
|
38, 01, 01,
|
|
33, 04, 01, 02, 03, 04,
|
|
54, 01, 06,
|
|
50, 01, 02,
|
|
5B, 01, 00,
|
|
3E, 01, 00,
|
|
80, 01, 01,
|
|
81, 01, 01,
|
|
82, 01, 0E,
|
|
18, 01, 01,
|
|
68, 01, 01,
|
|
85, 01, 01
|
|
}
|
|
###############################################################################
|
|
# Enable(0x01) or disable(0x00) non-standard tag reading
|
|
# Disable Non-standard card read 0x00
|
|
# Enable Non-standard card read 0x01
|
|
NXP_SUPPORT_NON_STD_CARD=0x00
|
|
#################################################################################
|
|
# Enable(0x01) or disable(0x00 ) for getting HW Info log over SMB wired
|
|
# Disable getting HW info log 0x00
|
|
# Enable getting HW info log 0x01
|
|
NXP_GET_HW_INFO_LOG=0x00
|
|
#################################################################################
|
|
# Enable(0x01) or disable(0x00) iso dep sak merge
|
|
# Disable SAK merging 0x00
|
|
# Enable SAK merging 0x01
|
|
NXP_ISO_DEP_MERGE_SAK=0x01
|
|
#################################################################################
|
|
# Valid time difference range within for non-standard tag detection from first
|
|
# Activation fail to next discovery
|
|
# Note :- 1. This will take effect only when NXP_SUPPORT_NON_STD_CARD is enabled
|
|
# 2. The number will be multiplied by 100ms by MW.
|
|
# Default:
|
|
# Set to 00 if not supported
|
|
# byte[0] MIFARE_CLASSIC 100ms
|
|
# byte[1] ISO_DEP 300ms
|
|
NXP_NON_STD_CARD_TIMEDIFF={01, 03}
|
|
#################################################################################
|
|
# Enable or Disable UICC ETSI support
|
|
# Disable UICC ETSI support 0
|
|
# Enable UICC ETSI support 1
|
|
NXP_UICC_ETSI_SUPPORT=0
|
|
#################################################################################
|
|
# Enable Stop/Start of RF discovery for NFCEE recovery
|
|
# Disable RF Restart for NFCEE recovery 0
|
|
# Enable RF Restart for NFCEE recovery 1
|
|
NXP_RESTART_RF_FOR_NFCEE_RECOVERY=0
|
|
#################################################################################
|
|
#Tag Presence check timeout in millisecond.
|
|
NXP_PRESENCE_CHECK_TIMEOUT = 375
|
|
|
|
|