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Rtwo/kernel/motorola/sm8550-devicetrees/qcom/direwolf-vm-pcie.dtsi

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initial android 16 commit
2025-09-30 20:22:48 -04:00
&soc {
pcie0: qcom,pcie@0x1c20000 {
compatible = "qcom,pci-msm";
reg = <0x01c20000 0x3000>,
<0x01c24000 0x2000>,
<0x3c000000 0xf1d>,
<0x3c000f20 0xa8>,
<0x3c001000 0x1000>,
<0x3c100000 0x100000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
cell-index = <0>;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x3c200000 0x3c200000 0x0 0x100000>,
<0x02000000 0x0 0x3c300000 0x3c300000 0x0 0x1d00000>;
interrupt-parent = <&pcie0>;
interrupts = <0 1 2 3 4>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 0 &intc GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0x0 &virt_smmuv3 0x20000 0x10000>;
msi-parent = <&pcie2a_msi_snps>;
perst-gpio = <&tlmm 143 0>;
wake-gpio = <&tlmm 145 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2a_perst_default
&pcie2a_clkreq_default
&pcie2a_wake_default>;
gdsc-core-vdd-supply = <&gcc_pcie_2a_gdsc>;
vreg-1p2-supply = <&L3A0>;
vreg-0p9-supply = <&L11A0>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
qcom,vreg-1p2-voltage-level = <1200000 1200000 25000>;
qcom,vreg-0p9-voltage-level = <880000 880000 99000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
clocks = <&gcc GCC_PCIE_2A_PIPE_CLK>,
<&rpmh_cxo_clk>,
<&gcc GCC_PCIE_2A_AUX_CLK>,
<&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
<&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
<&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
<&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
<&gcc GCC_PCIE_2A_PIPE_CLK_SRC>,
<&pcie_2a_pipe_clk>,
<&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
<&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
clock-names = "pcie_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
"pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src",
"pcie_aggre_noc_south_sf_axi_clk", "pcie_0_pipediv2_clk";
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>, <0>, <0>;
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_2A_BCR>,
<&gcc GCC_PCIE_2A_PHY_BCR>,
<&gcc GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR>;
reset-names = "pcie_0_core_reset",
"pcie_0_phy_reset",
"pcie_phy_nocsr_com_phy_reset";
dma-coherent;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <70>;
qcom,slv-addr-space-size = <0x2000000>;
qcom,ep-latency = <10>;
qcom,core-preset = <0x77777777>;
qcom,no-l1ss-supported;
qcom,pcie-phy-ver = <1106>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x0044 0x14 0x0
0x0010 0x00 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x0048 0x90 0x0
0x0058 0x0f 0x0
0x0074 0x06 0x0
0x0078 0x06 0x0
0x007c 0x16 0x0
0x0080 0x16 0x0
0x0084 0x36 0x0
0x0088 0x36 0x0
0x0094 0x08 0x0
0x00a4 0x42 0x0
0x00ac 0x0a 0x0
0x00b0 0x1a 0x0
0x00b4 0x14 0x0
0x00b8 0x34 0x0
0x00bc 0x82 0x0
0x00c4 0x68 0x0
0x00cc 0x55 0x0
0x00d0 0x55 0x0
0x00d4 0x03 0x0
0x00d8 0xab 0x0
0x00dc 0xaa 0x0
0x00e0 0x02 0x0
0x010c 0x02 0x0
0x0110 0x24 0x0
0x0118 0xb4 0x0
0x011c 0x03 0x0
0x0154 0x34 0x0
0x0158 0x01 0x0
0x016c 0x08 0x0
0x01ac 0xb9 0x0
0x01b0 0x1e 0x0
0x01b4 0x94 0x0
0x01b8 0x18 0x0
0x01bc 0x11 0x0
0x0ee4 0x02 0x0
0x16e4 0x04 0x0
0x0e84 0xd5 0x0
0x1684 0xd5 0x0
0x0e90 0x3f 0x0
0x1690 0x3f 0x0
0x0e3c 0x11 0x0
0x163c 0x11 0x0
0x0e40 0x0c 0x0
0x1640 0x0c 0x0
0x115c 0x7f 0x0
0x1160 0xff 0x0
0x1164 0x7f 0x0
0x1168 0x34 0x0
0x116c 0xd8 0x0
0x195c 0x7f 0x0
0x1960 0xff 0x0
0x1964 0x7f 0x0
0x1968 0x34 0x0
0x196c 0xd8 0x0
0x1170 0xdc 0x0
0x1174 0xdc 0x0
0x1178 0x5c 0x0
0x117c 0x34 0x0
0x1180 0xa6 0x0
0x1970 0xdc 0x0
0x1974 0xdc 0x0
0x1978 0x5c 0x0
0x197c 0x34 0x0
0x1980 0xa6 0x0
0x1190 0x34 0x0
0x1990 0x34 0x0
0x10d8 0x0f 0x0
0x18d8 0x0f 0x0
0x10dc 0x00 0x0
0x18dc 0x00 0x0
0x104c 0x08 0x0
0x184c 0x08 0x0
0x1050 0x08 0x0
0x1850 0x08 0x0
0x1044 0xf0 0x0
0x1844 0xf0 0x0
0x11a4 0x38 0x0
0x19a4 0x38 0x0
0x02dc 0x05 0x0
0x0388 0x88 0x0
0x0398 0x0b 0x0
0x03e4 0x0f 0x0
0x060c 0x1d 0x0
0x0614 0x07 0x0
0x0620 0xc1 0x0
0x0694 0x00 0x0
0x0200 0x00 0x0
0x0244 0x03 0x0>;
status = "disabled";
pcie0_rp: pcie0_rp {
reg = <0 0 0 0 0>;
};
};
pcie1: qcom,pcie@0x01c18000 {
compatible = "qcom,pci-msm";
reg = <0x01c18000 0x3000>,
<0x01c1e000 0x2000>,
<0x38000000 0xf1d>,
<0x38000f20 0xa8>,
<0x38001000 0x1000>,
<0x38100000 0x100000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
cell-index = <1>;
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x38200000 0x38200000 0x0 0x100000>,
<0x02000000 0x0 0x38300000 0x38300000 0x0 0x1d00000>;
interrupt-parent = <&pcie1>;
interrupts = <0 1 2 3 4>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 0 &intc GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&pcie2b_msi_snps>;
perst-gpio = <&tlmm 147 0>;
wake-gpio = <&tlmm 146 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2b_perst_default
&pcie2b_clkreq_default
&pcie2b_wake_default>;
gdsc-core-vdd-supply = <&gcc_pcie_2b_gdsc>;
vreg-1p2-supply = <&L3A0>;
vreg-0p9-supply = <&L11A0>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
qcom,vreg-1p2-voltage-level = <1200000 1200000 25000>;
qcom,vreg-0p9-voltage-level = <880000 880000 99000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
clocks = <&gcc GCC_PCIE_2B_PIPE_CLK>,
<&rpmh_cxo_clk>,
<&gcc GCC_PCIE_2B_AUX_CLK>,
<&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
<&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
<&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
<&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
<&gcc GCC_PCIE_2B_PIPE_CLK_SRC>,
<&pcie_2b_pipe_clk>,
<&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
<&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
clock-names = "pcie_pipe_clk", "pcie_1_ref_clk_src",
"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
"pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src",
"pcie_aggre_noc_south_sf_axi_clk", "pcie_1_pipediv2_clk";
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>, <0>, <0>;
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_2B_BCR>,
<&gcc GCC_PCIE_2B_PHY_BCR>,
<&gcc GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR>;
reset-names = "pcie_1_core_reset",
"pcie_1_phy_reset",
"pcie_phy_nocsr_com_phy_reset";
dma-coherent;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <70>;
qcom,slv-addr-space-size = <0x2000000>;
qcom,ep-latency = <10>;
qcom,core-preset = <0x77777777>;
qcom,no-l1ss-supported;
qcom,pcie-phy-ver = <1106>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x0044 0x14 0x0
0x0010 0x00 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x0048 0x90 0x0
0x0058 0x0f 0x0
0x0074 0x06 0x0
0x0078 0x06 0x0
0x007c 0x16 0x0
0x0080 0x16 0x0
0x0084 0x36 0x0
0x0088 0x36 0x0
0x0094 0x08 0x0
0x00a4 0x42 0x0
0x00ac 0x0a 0x0
0x00b0 0x1a 0x0
0x00b4 0x14 0x0
0x00b8 0x34 0x0
0x00bc 0x82 0x0
0x00c4 0x68 0x0
0x00cc 0x55 0x0
0x00d0 0x55 0x0
0x00d4 0x03 0x0
0x00d8 0xab 0x0
0x00dc 0xaa 0x0
0x00e0 0x02 0x0
0x010c 0x02 0x0
0x0110 0x24 0x0
0x0118 0xb4 0x0
0x011c 0x03 0x0
0x0154 0x34 0x0
0x0158 0x01 0x0
0x016c 0x08 0x0
0x01ac 0xb9 0x0
0x01b0 0x1e 0x0
0x01b4 0x94 0x0
0x01b8 0x18 0x0
0x01bc 0x11 0x0
0x0ee4 0x02 0x0
0x16e4 0x04 0x0
0x0e84 0xd5 0x0
0x1684 0xd5 0x0
0x0e90 0x3f 0x0
0x1690 0x3f 0x0
0x0e3c 0x11 0x0
0x163c 0x11 0x0
0x0e40 0x0c 0x0
0x1640 0x0c 0x0
0x115c 0x7f 0x0
0x1160 0xff 0x0
0x1164 0x7f 0x0
0x1168 0x34 0x0
0x116c 0xd8 0x0
0x195c 0x7f 0x0
0x1960 0xff 0x0
0x1964 0x7f 0x0
0x1968 0x34 0x0
0x196c 0xd8 0x0
0x1170 0xdc 0x0
0x1174 0xdc 0x0
0x1178 0x5c 0x0
0x117c 0x34 0x0
0x1180 0xa6 0x0
0x1970 0xdc 0x0
0x1974 0xdc 0x0
0x1978 0x5c 0x0
0x197c 0x34 0x0
0x1980 0xa6 0x0
0x1190 0x34 0x0
0x1990 0x34 0x0
0x10d8 0x0f 0x0
0x18d8 0x0f 0x0
0x10dc 0x00 0x0
0x18dc 0x00 0x0
0x104c 0x08 0x0
0x184c 0x08 0x0
0x1050 0x08 0x0
0x1850 0x08 0x0
0x1044 0xf0 0x0
0x1844 0xf0 0x0
0x11a4 0x38 0x0
0x19a4 0x38 0x0
0x02dc 0x05 0x0
0x0388 0x88 0x0
0x0398 0x0b 0x0
0x03e4 0x0f 0x0
0x060c 0x1d 0x0
0x0614 0x07 0x0
0x0620 0xc1 0x0
0x0694 0x00 0x0
0x0200 0x00 0x0
0x0244 0x03 0x0>;
status = "disabled";
pcie1_rp: pcie1_rp {
reg = <0 0 0 0 0>;
};
};
pcie2: qcom,pcie@0x1c10000 {
compatible = "qcom,pci-msm";
reg = <0x01c10000 0x3000>,
<0x01c14000 0x2000>,
<0x40000000 0xf1d>,
<0x40000f20 0xa8>,
<0x40001000 0x1000>,
<0x40100000 0x100000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
cell-index = <2>;
linux,pci-domain = <2>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1d00000>;
interrupt-parent = <&pcie2>;
interrupts = <0 1 2 3 4>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 &intc 0 GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&pcie3a_msi_snps>;
perst-gpio = <&tlmm 151 0>;
wake-gpio = <&tlmm 56 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3a_perst_default
&pcie3a_clkreq_default
&pcie3a_wake_default>;
gdsc-core-vdd-supply = <&gcc_pcie_3a_gdsc>;
vreg-1p2-supply = <&L3A0>;
vreg-0p9-supply = <&L11A0>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
qcom,vreg-1p2-voltage-level = <1200000 1200000 25000>;
qcom,vreg-0p9-voltage-level = <880000 880000 99000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
clocks = <&gcc GCC_PCIE_3A_PIPE_CLK>,
<&rpmh_cxo_clk>,
<&gcc GCC_PCIE_3A_AUX_CLK>,
<&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
<&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
<&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
<&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
<&gcc GCC_PCIE_3A_PIPE_CLK_SRC>,
<&pcie_3a_pipe_clk>,
<&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
<&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
clock-names = "pcie_pipe_clk", "pcie_2_ref_clk_src",
"pcie_2_aux_clk", "pcie_2_cfg_ahb_clk",
"pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk",
"pcie_2_ldo", "pcie_2_slv_q2a_axi_clk",
"pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src",
"pcie_aggre_noc_south_sf_axi_clk", "pcie_2_pipediv2_clk";
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>, <0>, <0>;
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_3A_BCR>,
<&gcc GCC_PCIE_3A_PHY_BCR>,
<&gcc GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR>;
reset-names = "pcie_2_core_reset",
"pcie_2_phy_reset",
"pcie_phy_nocsr_com_phy_reset";
dma-coherent;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <70>;
qcom,slv-addr-space-size = <0x2000000>;
qcom,ep-latency = <10>;
qcom,core-preset = <0x77777777>;
qcom,no-l1ss-supported;
qcom,pcie-phy-ver = <1106>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x0010 0x01 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x0048 0x90 0x0
0x0058 0x0f 0x0
0x0074 0x06 0x0
0x0078 0x06 0x0
0x007c 0x16 0x0
0x0080 0x16 0x0
0x0084 0x36 0x0
0x0088 0x36 0x0
0x0094 0x08 0x0
0x00a4 0x42 0x0
0x00ac 0x0a 0x0
0x00b0 0x1a 0x0
0x00b4 0x14 0x0
0x00b8 0x34 0x0
0x00bc 0x82 0x0
0x00c4 0x68 0x0
0x00cc 0x55 0x0
0x00d0 0x55 0x0
0x00d4 0x03 0x0
0x00d8 0xab 0x0
0x00dc 0xaa 0x0
0x00e0 0x02 0x0
0x010c 0x02 0x0
0x0110 0x24 0x0
0x0118 0xb4 0x0
0x011c 0x03 0x0
0x0154 0x34 0x0
0x0158 0x01 0x0
0x016c 0x08 0x0
0x01ac 0xca 0x0
0x01b0 0x1e 0x0
0x01b4 0xa2 0x0
0x01b8 0x18 0x0
0x01bc 0x11 0x0
0x0ee4 0x02 0x0
0x16e4 0x04 0x0
0x1684 0xd5 0x0
0x0e84 0xd5 0x0
0x1690 0x3f 0x0
0x0e90 0x3f 0x0
0x115c 0x7f 0x0
0x1160 0xff 0x0
0x1164 0x7f 0x0
0x1168 0x34 0x0
0x116c 0xd8 0x0
0x1170 0xdc 0x0
0x1174 0xdc 0x0
0x1178 0x5c 0x0
0x117c 0x34 0x0
0x1180 0xa6 0x0
0x195c 0x7f 0x0
0x1960 0xff 0x0
0x1964 0x7f 0x0
0x1968 0x34 0x0
0x196c 0xd8 0x0
0x1970 0xdc 0x0
0x1974 0xdc 0x0
0x1978 0x5c 0x0
0x197c 0x34 0x0
0x1980 0xa6 0x0
0x10cc 0xf0 0x0
0x18cc 0xf0 0x0
0x10d8 0x0f 0x0
0x18d8 0x0f 0x0
0x10dc 0x00 0x0
0x18dc 0x00 0x0
0x11a4 0x38 0x0
0x19a4 0x38 0x0
0x0e3c 0x1d 0x0
0x163c 0x1d 0x0
0x0e40 0x0c 0x0
0x1640 0x0c 0x0
0x1190 0x34 0x0
0x1990 0x34 0x0
0x104c 0x08 0x0
0x184c 0x08 0x0
0x1050 0x08 0x0
0x1850 0x08 0x0
0x02dc 0x05 0x0
0x0388 0x77 0x0
0x0398 0x0b 0x0
0x03e0 0x0f 0x0
0x060c 0x1d 0x0
0x0614 0x07 0x0
0x0620 0xc1 0x0
0x0694 0x00 0x0
0x0200 0x00 0x0
0x0244 0x03 0x0>;
status = "disabled";
pcie2_rp: pcie2_rp {
reg = <0 0 0 0 0>;
};
};
pcie3: qcom,pcie@0x01c08000 {
compatible = "qcom,pci-msm";
reg = <0x01c08000 0x3000>,
<0x01c0e000 0x2000>,
<0x32000000 0xf1d>,
<0x32000f20 0xa8>,
<0x32001000 0x1000>,
<0x32100000 0x100000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
cell-index = <3>;
linux,pci-domain = <3>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x32200000 0x32200000 0x0 0x100000>,
<0x02000000 0x0 0x32300000 0x32300000 0x0 0x1d00000>;
interrupt-parent = <&pcie3>;
interrupts = <0 1 2 3 4>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 0 &intc GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&pcie3b_msi_snps>;
perst-gpio = <&tlmm 153 0>;
wake-gpio = <&tlmm 130 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3b_perst_default
&pcie3b_clkreq_default
&pcie3b_wake_default>;
gdsc-core-vdd-supply = <&gcc_pcie_3b_gdsc>;
vreg-1p2-supply = <&L3A0>;
vreg-0p9-supply = <&L11A0>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
qcom,vreg-1p2-voltage-level = <1200000 1200000 25000>;
qcom,vreg-0p9-voltage-level = <880000 880000 99000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
clocks = <&gcc GCC_PCIE_3B_PIPE_CLK>,
<&rpmh_cxo_clk>,
<&gcc GCC_PCIE_3B_AUX_CLK>,
<&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
<&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
<&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
<&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
<&gcc GCC_PCIE_3B_PIPE_CLK_SRC>,
<&pcie_3b_pipe_clk>,
<&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
<&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
clock-names = "pcie_pipe_clk", "pcie_3_ref_clk_src",
"pcie_3_aux_clk", "pcie_3_cfg_ahb_clk",
"pcie_3_mstr_axi_clk", "pcie_3_slv_axi_clk",
"pcie_3_ldo", "pcie_3_slv_q2a_axi_clk",
"pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src",
"pcie_aggre_noc_south_sf_axi_clk", "pcie_3_pipediv2_clk";
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>, <0>, <0>;
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_3B_BCR>,
<&gcc GCC_PCIE_3B_PHY_BCR>,
<&gcc GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR>;
reset-names = "pcie_3_core_reset",
"pcie_3_phy_reset",
"pcie_phy_nocsr_com_phy_reset";
dma-coherent;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <70>;
qcom,slv-addr-space-size = <0x2000000>;
qcom,ep-latency = <10>;
qcom,core-preset = <0x77777777>;
qcom,no-l1ss-supported;
qcom,pcie-phy-ver = <1106>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x0044 0x14 0x0
0x0010 0x00 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x0048 0x90 0x0
0x0058 0x0f 0x0
0x0074 0x06 0x0
0x0078 0x06 0x0
0x007c 0x16 0x0
0x0080 0x16 0x0
0x0084 0x36 0x0
0x0088 0x36 0x0
0x0094 0x08 0x0
0x00a4 0x42 0x0
0x00ac 0x0a 0x0
0x00b0 0x1a 0x0
0x00b4 0x14 0x0
0x00b8 0x34 0x0
0x00bc 0x82 0x0
0x00c4 0x68 0x0
0x00cc 0x55 0x0
0x00d0 0x55 0x0
0x00d4 0x03 0x0
0x00d8 0xab 0x0
0x00dc 0xaa 0x0
0x00e0 0x02 0x0
0x010c 0x02 0x0
0x0110 0x24 0x0
0x0118 0xb4 0x0
0x011c 0x03 0x0
0x0154 0x34 0x0
0x0158 0x01 0x0
0x016c 0x08 0x0
0x01ac 0xb9 0x0
0x01b0 0x1e 0x0
0x01b4 0x94 0x0
0x01b8 0x18 0x0
0x01bc 0x11 0x0
0x0ee4 0x02 0x0
0x16e4 0x04 0x0
0x0e84 0xd5 0x0
0x1684 0xd5 0x0
0x0e90 0x3f 0x0
0x1690 0x3f 0x0
0x0e3c 0x11 0x0
0x163c 0x11 0x0
0x0e40 0x0c 0x0
0x1640 0x0c 0x0
0x115c 0x7f 0x0
0x1160 0xff 0x0
0x1164 0x7f 0x0
0x1168 0x34 0x0
0x116c 0xd8 0x0
0x195c 0x7f 0x0
0x1960 0xff 0x0
0x1964 0x7f 0x0
0x1968 0x34 0x0
0x196c 0xd8 0x0
0x1170 0xdc 0x0
0x1174 0xdc 0x0
0x1178 0x5c 0x0
0x117c 0x34 0x0
0x1180 0xa6 0x0
0x1970 0xdc 0x0
0x1974 0xdc 0x0
0x1978 0x5c 0x0
0x197c 0x34 0x0
0x1980 0xa6 0x0
0x1190 0x34 0x0
0x1990 0x34 0x0
0x10d8 0x0f 0x0
0x18d8 0x0f 0x0
0x10dc 0x00 0x0
0x18dc 0x00 0x0
0x104c 0x08 0x0
0x184c 0x08 0x0
0x1050 0x08 0x0
0x1850 0x08 0x0
0x1044 0xf0 0x0
0x1844 0xf0 0x0
0x11a4 0x38 0x0
0x19a4 0x38 0x0
0x02dc 0x05 0x0
0x0388 0x88 0x0
0x0398 0x0b 0x0
0x03e4 0x0f 0x0
0x060c 0x1d 0x0
0x0614 0x07 0x0
0x0620 0xc1 0x0
0x0694 0x00 0x0
0x0200 0x00 0x0
0x0244 0x03 0x0>;
status = "disabled";
pcie3_rp: pcie3_rp {
reg = <0 0 0 0 0>;
};
};
pcie4: qcom,pcie@1c00000 {
compatible = "qcom,pci-msm";
reg = <0x01c00000 0x3000>,
<0x01c06000 0x2000>,
<0x30000000 0xf1d>,
<0x30000f20 0xa8>,
<0x30001000 0x1000>,
<0x30100000 0x100000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
cell-index = <4>;
linux,pci-domain = <4>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x30200000 0x30200000 0x0 0x100000>,
<0x02000000 0x0 0x30300000 0x30300000 0x0 0x1d00000>;
interrupt-parent = <&pcie4>;
interrupts = <0 1 2 3 4>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 0 &intc GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0x0 &virt_smmuv3 0x60000 0x10000>;
msi-parent = <&pcie4_msi_snps>;
qcom,target-link-speed = <0x3>;
qcom,core-preset = <0x77777777>;
qcom,no-l1ss-supported;
perst-gpio = <&tlmm 141 0>;
wake-gpio = <&tlmm 139 0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie4_perst_default
&pcie4_clkreq_default
&pcie4_wake_default>;
pinctrl-1 = <&pcie4_perst_default
&pcie4_clkreq_sleep
&pcie4_wake_default>;
gdsc-core-vdd-supply = <&gcc_pcie_4_gdsc>;
vreg-1p2-supply = <&L3A0>;
vreg-0p9-supply = <&L11A0>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
qcom,vreg-1p2-voltage-level = <1200000 1200000 25000>;
qcom,vreg-0p9-voltage-level = <880000 880000 97200>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
clocks = <&gcc GCC_PCIE_4_PIPE_CLK>,
<&rpmh_cxo_clk>,
<&gcc GCC_PCIE_4_AUX_CLK>,
<&gcc GCC_PCIE_4_CFG_AHB_CLK>,
<&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_4_SLV_AXI_CLK>,
<&gcc GCC_PCIE_4_CLKREF_CLK>,
<&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
<&gcc GCC_PCIE_4_PIPE_CLK_SRC>,
<&pcie_4_pipe_clk>,
<&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
<&gcc GCC_CNOC_PCIE4_QX_CLK>,
<&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
clock-names = "pcie_pipe_clk", "pcie_4_ref_clk_src",
"pcie_4_aux_clk", "pcie_4_cfg_ahb_clk",
"pcie_4_mstr_axi_clk", "pcie_4_slv_axi_clk",
"pcie_4_ldo", "pcie_4_slv_q2a_axi_clk",
"pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src",
"pcie_aggre_noc_south_sf_axi_clk", "pcie_cnoc_4_qx",
"pcie_4_pipediv2_clk";
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>, <0>, <0>, <0>;
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_4_BCR>,
<&gcc GCC_PCIE_4_PHY_BCR>,
<&gcc GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR>;
reset-names = "pcie_4_core_reset",
"pcie_4_phy_reset",
"pcie_phy_nocsr_com_phy_reset";
dma-coherent;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <70>;
qcom,slv-addr-space-size = <0x2000000>;
qcom,ep-latency = <10>;
qcom,pcie-phy-ver = <10102>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x0094 0x08 0x0
0x0154 0x34 0x0
0x016c 0x08 0x0
0x0058 0x0f 0x0
0x00a4 0x42 0x0
0x0110 0x24 0x0
0x011c 0x03 0x0
0x0118 0xb4 0x0
0x010c 0x02 0x0
0x01bc 0x11 0x0
0x00bc 0x82 0x0
0x00d4 0x03 0x0
0x00d0 0x55 0x0
0x00cc 0x55 0x0
0x00b0 0x1a 0x0
0x00ac 0x0a 0x0
0x00c4 0x68 0x0
0x00e0 0x02 0x0
0x00dc 0xaa 0x0
0x00d8 0xab 0x0
0x00b8 0x34 0x0
0x00b4 0x14 0x0
0x0158 0x01 0x0
0x0074 0x06 0x0
0x007c 0x16 0x0
0x0084 0x36 0x0
0x0078 0x06 0x0
0x0080 0x16 0x0
0x0088 0x36 0x0
0x01b0 0x1e 0x0
0x01ac 0xb9 0x0
0x01b8 0x18 0x0
0x01b4 0x94 0x0
0x0050 0x07 0x0
0x0010 0x00 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x0ee4 0x20 0x0
0x0e84 0x75 0x0
0x0e90 0x3f 0x0
0x115c 0x7f 0x0
0x1160 0xff 0x0
0x1164 0xbf 0x0
0x1168 0x3f 0x0
0x116c 0xd8 0x0
0x1170 0xdc 0x0
0x1174 0xdc 0x0
0x1178 0x5c 0x0
0x117c 0x34 0x0
0x1180 0xa6 0x0
0x1190 0x34 0x0
0x10d8 0x07 0x0
0x0e3c 0x1d 0x0
0x0e40 0x0c 0x0
0x10dc 0x00 0x0
0x104c 0x08 0x0
0x1050 0x08 0x0
0x1044 0xf0 0x0
0x11a4 0x38 0x0
0x10cc 0xf0 0x0
0x0694 0x00 0x0
0x0654 0x00 0x0
0x06a8 0x0f 0x0
0x0048 0x90 0x0
0x0620 0xc1 0x0
0x0388 0x77 0x0
0x0398 0x0b 0x0
0x02dc 0x05 0x0
0x0200 0x00 0x0
0x0244 0x03 0x0>;
status = "disabled";
pcie4_rp: pcie4_rp {
reg = <0 0 0 0 0>;
};
};
pcie2a_msi_snps: qcom,pcie2a_msi@a0000000 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0xa0000000 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
qcom,snps;
status = "disabled";
};
pcie2b_msi_snps: qcom,pcie2b_msi@a0000000 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0xa0000000 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
qcom,snps;
status = "disabled";
};
pcie3a_msi_snps: qcom,pcie3a_msi@a0000000 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0xa0000000 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
qcom,snps;
status = "disabled";
};
pcie3b_msi_snps: qcom,pcie3b_msi@a0000000 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0xa0000000 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
qcom,snps;
status = "disabled";
};
pcie4_msi_snps: qcom,pcie4_msi@a0000000 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0xa0000000 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
qcom,snps;
status = "disabled";
};
};
Reference in a new issue Copy permalink