Rtwo/kernel/motorola/sm8550-devicetrees/qcom/kaka.dtsi

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Qualcomm Technologies, Inc. Kaka";
	compatible = "qcom,kaka";
	qcom,msm-id = <519 0x10000>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;
	memory { device_type = "memory"; reg = <0 0 0 0>; };

	chosen: chosen { };

	aliases { };

	cpus {
			#address-cells = <2>;
			#size-cells = <0>;

			CPU0: cpu@0 {
				device_type = "cpu";
				compatible = "qcom,kryo";
				reg = <0x0 0x0>;
				enable-method = "spin-table";
				cpu-release-addr = <0x0 0x90000000>;
				next-level-cache = <&L2_0>;
				L2_0: l2-cache {
						compatible = "arm,arch-cache";
						cache-level = <2>;
						next-level-cache = <&L3_0>;
					L3_0: l3-cache {
							compatible = "arm,arch-cache";
							cache-level = <3>;
					};
				};
			};

			CPU1: cpu@100 {
				device_type = "cpu";
				compatible = "qcom,kryo";
				reg = <0x0 0x100>;
				enable-method = "spin-table";
				cpu-release-addr = <0x0 0x90000000>;
				next-level-cache = <&L2_1>;
				L2_1: l2-cache {
						compatible = "arm,arch-cache";
						cache-level = <2>;
						next-level-cache = <&L3_0>;
				};
			};

			CPU2: cpu@200 {
				device_type = "cpu";
				compatible = "qcom,kryo";
				reg = <0x0 0x200>;
				enable-method = "spin-table";
				cpu-release-addr = <0x0 0x90000000>;
				next-level-cache = <&L2_2>;
				L2_2: l2-cache {
						compatible = "arm,arch-cache";
						cache-level = <2>;
						next-level-cache = <&L3_0>;
				};
			};

			CPU3: cpu@300 {
				device_type = "cpu";
				compatible = "qcom,kryo";
				reg = <0x0 0x300>;
				enable-method = "spin-table";
				cpu-release-addr = <0x0 0x90000000>;
				next-level-cache = <&L2_3>;
				L2_3: l2-cache {
						compatible = "arm,arch-cache";
						cache-level = <2>;
						next-level-cache = <&L3_0>;
				};
			};

			CPU4: cpu@400 {
				device_type = "cpu";
				compatible = "qcom,kryo";
				reg = <0x0 0x400>;
				enable-method = "spin-table";
				cpu-release-addr = <0x0 0x90000000>;
				next-level-cache = <&L2_4>;
				L2_4: l2-cache {
					compatible = "arm,arch-cache";
					cache-level = <2>;
					next-level-cache = <&L3_0>;
				};
			};

			CPU5: cpu@500 {
				device_type = "cpu";
				compatible = "qcom,kryo";
				reg = <0x0 0x500>;
				enable-method = "spin-table";
				cpu-release-addr = <0x0 0x90000000>;
				next-level-cache = <&L2_5>;
				L2_5: l2-cache {
					compatible = "arm,arch-cache";
					cache-level = <2>;
					next-level-cache = <&L3_0>;
				};
			};

			CPU6: cpu@600 {
				device_type = "cpu";
				compatible = "qcom,kryo";
				reg = <0x0 0x600>;
				enable-method = "spin-table";
				cpu-release-addr = <0x0 0x90000000>;
				next-level-cache = <&L2_6>;
				L2_6: l2-cache {
					compatible = "arm,arch-cache";
					cache-level = <2>;
					next-level-cache = <&L3_0>;
					};
			};

			CPU7: cpu@700 {
				device_type = "cpu";
				compatible = "qcom,kryo";
				reg = <0x0 0x700>;
				enable-method = "spin-table";
				cpu-release-addr = <0x0 0x90000000>;
				next-level-cache = <&L2_7>;
				L2_7: l2-cache {
					compatible = "arm,arch-cache";
					cache-level = <2>;
					next-level-cache = <&L3_0>;
				};
			};

			cpu-map {
				cluster0 {
					core0 {
						cpu = <&CPU0>;
					};

					core1 {
						cpu = <&CPU1>;
					};

					core2 {
						cpu = <&CPU2>;
					};

					core3 {
						cpu = <&CPU3>;
					};
				};

				cluster1 {
					core0 {
						cpu = <&CPU4>;
					};

					core1 {
						cpu = <&CPU5>;
					};

					core2 {
						cpu = <&CPU6>;
					};
				};

				cluster2 {
					core0 {
						cpu = <&CPU7>;
					};
				};
		};
	};

	soc: soc { };
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@17100000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x40000>;
		reg = <0x17100000 0x10000>,/* GICD */
			<0x17180000 0x200000>;/* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
					<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
					<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
					<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	memtimer: timer@17420000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17420000 0x1000>;
		clock-frequency = <19200000>;

		frame@17421000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17421000 0x1000>,
				<0x17422000 0x1000>;
		};

		frame@17423000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17423000 0x1000>;
			status = "disabled";
		};

		frame@17425000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17425000 0x1000>;
			status = "disabled";
		};

		frame@17427000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17427000 0x1000>;
			status = "disabled";
		};

		frame@17429000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17429000 0x1000>;
			status = "disabled";
		};

		frame@1742b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742b000 0x1000>;
			status = "disabled";
		};

		frame@1742d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742d000 0x1000>;
			status = "disabled";
		};
	};
};