331 lines
7.8 KiB
Text
331 lines
7.8 KiB
Text
|
&soc {
|
||
|
|
/* CAM_CC GDSCs */
|
||
|
|
cam_cc_camss_top_gdsc: qcom,gdsc@add5004 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xadd5004 0x4>;
|
||
|
|
regulator-name = "cam_cc_camss_top_gdsc";
|
||
|
|
qcom,retain-regs;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_cc_bps_gdsc: qcom,gdsc@adf0004 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xadf0004 0x4>;
|
||
|
|
regulator-name = "cam_cc_bps_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,support-hw-trigger;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_cc_ife_0_gdsc: qcom,gdsc@adf1004 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xadf1004 0x4>;
|
||
|
|
regulator-name = "cam_cc_ife_0_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_cc_ife_1_gdsc: qcom,gdsc@adf2004 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xadf2004 0x4>;
|
||
|
|
regulator-name = "cam_cc_ife_1_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_cc_ife_2_gdsc: qcom,gdsc@adf2294 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xadf2294 0x4>;
|
||
|
|
regulator-name = "cam_cc_ife_2_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_cc_ipe_0_gdsc: qcom,gdsc@adf03b8 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xadf03b8 0x4>;
|
||
|
|
regulator-name = "cam_cc_ipe_0_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,support-hw-trigger;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_cc_sbi_gdsc: qcom,gdsc@adf052c {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xadf052c 0x4>;
|
||
|
|
regulator-name = "cam_cc_sbi_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_cc_sfe_0_gdsc: qcom,gdsc@adf3280 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xadf3280 0x4>;
|
||
|
|
regulator-name = "cam_cc_sfe_0_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_cc_sfe_1_gdsc: qcom,gdsc@adf33e0 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xadf33e0 0x4>;
|
||
|
|
regulator-name = "cam_cc_sfe_1_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_cc_titan_top_gdsc: qcom,gdsc@adf4058 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xadf4058 0x4>;
|
||
|
|
regulator-name = "cam_cc_titan_top_gdsc";
|
||
|
|
proxy-supply = <&cam_cc_titan_top_gdsc>;
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,proxy-consumer-enable;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* DISP_CC GDSCs */
|
||
|
|
disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xaf09000 0x4>;
|
||
|
|
regulator-name = "disp_cc_mdss_core_gdsc";
|
||
|
|
proxy-supply = <&disp_cc_mdss_core_gdsc>;
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,proxy-consumer-enable;
|
||
|
|
qcom,support-hw-trigger;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xaf0b000 0x4>;
|
||
|
|
regulator-name = "disp_cc_mdss_core_int2_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,support-hw-trigger;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gcc_apcs_gdsc_vote_ctrl: syscon@152020 {
|
||
|
|
compatible = "syscon";
|
||
|
|
reg = <0x152020 0x4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gcc_apcs_gdsc_sleep_ctrl: syscon@152024 {
|
||
|
|
compatible = "syscon";
|
||
|
|
reg = <0x152024 0x4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* GCC GDSCs */
|
||
|
|
gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0x16b004 0x4>;
|
||
|
|
regulator-name = "gcc_pcie_0_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,no-status-check-on-disable;
|
||
|
|
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0x16c000 0x4>;
|
||
|
|
regulator-name = "gcc_pcie_0_phy_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,no-status-check-on-disable;
|
||
|
|
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 3>;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gcc_pcie_1_gdsc: qcom,gdsc@18d004 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0x18d004 0x4>;
|
||
|
|
regulator-name = "gcc_pcie_1_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,no-status-check-on-disable;
|
||
|
|
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gcc_pcie_1_phy_gdsc: qcom,gdsc@18e000 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0x18e000 0x4>;
|
||
|
|
regulator-name = "gcc_pcie_1_phy_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,no-status-check-on-disable;
|
||
|
|
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 4>;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0x19e000 0x4>;
|
||
|
|
regulator-name = "gcc_ufs_mem_phy_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0x177004 0x4>;
|
||
|
|
regulator-name = "gcc_ufs_phy_gdsc";
|
||
|
|
proxy-supply = <&gcc_ufs_phy_gdsc>;
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,proxy-consumer-enable;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gcc_usb30_prim_gdsc: qcom,gdsc@139004 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0x139004 0x4>;
|
||
|
|
regulator-name = "gcc_usb30_prim_gdsc";
|
||
|
|
proxy-supply = <&gcc_usb30_prim_gdsc>;
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,proxy-consumer-enable;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gcc_usb3_phy_gdsc: qcom,gdsc@150018 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0x150018 0x4>;
|
||
|
|
regulator-name = "gcc_usb3_phy_gdsc";
|
||
|
|
proxy-supply = <&gcc_usb3_phy_gdsc>;
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,proxy-consumer-enable;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* GPU_CC GDSCs */
|
||
|
|
gpu_cc_cx_gdsc_hw_ctrl: syscon@3d9953c {
|
||
|
|
compatible = "syscon";
|
||
|
|
reg = <0x3d9953c 0x4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0x3d99108 0x4>;
|
||
|
|
regulator-name = "gpu_cc_cx_gdsc";
|
||
|
|
hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>;
|
||
|
|
qcom,no-status-check-on-disable;
|
||
|
|
qcom,clk-dis-wait-val = <8>;
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpu_cc_gx_domain_addr: syscon@3d99504 {
|
||
|
|
compatible = "syscon";
|
||
|
|
reg = <0x3d99504 0x4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpu_cc_gx_sw_reset: syscon@3d99058 {
|
||
|
|
compatible = "syscon";
|
||
|
|
reg = <0x3d99058 0x4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpu_cc_gx_acd_reset: syscon@3d99358 {
|
||
|
|
compatible = "syscon";
|
||
|
|
reg = <0x3d99358 0x4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpu_cc_gx_acd_iroot_reset: syscon@3d9958c {
|
||
|
|
compatible = "syscon";
|
||
|
|
reg = <0x3d9958c 0x4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpu_cc_gx_gdsc: qcom,gdsc@3d9905c {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0x3d9905c 0x4>;
|
||
|
|
regulator-name = "gpu_cc_gx_gdsc";
|
||
|
|
domain-addr = <&gpu_cc_gx_domain_addr>;
|
||
|
|
sw-reset = <&gpu_cc_gx_sw_reset>,
|
||
|
|
<&gpu_cc_gx_acd_reset>,
|
||
|
|
<&gpu_cc_gx_acd_iroot_reset>;
|
||
|
|
qcom,reset-aon-logic;
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* VIDEO_CC GDSCs */
|
||
|
|
video_cc_mvs0_gdsc: qcom,gdsc@abf80a4 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xabf80a4 0x4>;
|
||
|
|
regulator-name = "video_cc_mvs0_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,support-hw-trigger;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
video_cc_mvs0c_gdsc: qcom,gdsc@abf804c {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xabf804c 0x4>;
|
||
|
|
regulator-name = "video_cc_mvs0c_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
video_cc_mvs1_gdsc: qcom,gdsc@abf80cc {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xabf80cc 0x4>;
|
||
|
|
regulator-name = "video_cc_mvs1_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,support-hw-trigger;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
video_cc_mvs1c_gdsc: qcom,gdsc@abf8078 {
|
||
|
|
compatible = "qcom,gdsc";
|
||
|
|
reg = <0xabf8078 0x4>;
|
||
|
|
regulator-name = "video_cc_mvs1c_gdsc";
|
||
|
|
qcom,gds-timeout = <1500>;
|
||
|
|
qcom,retain-regs;
|
||
|
|
qcom,support-cfg-gdscr;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|