Rtwo/kernel/motorola/sm8550-devicetrees/qcom/qcs405-cpu.dtsi

/ {
	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: cpu-pd0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD1: cpu-pd1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD2: cpu-pd2 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD3: cpu-pd3 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CLUSTER_PD: cluster-pd0 {
			#power-domain-cells = <0>;
			domain-idle-states = <&SILVER_CLUSTER_D3>;
		};
	};

	idle-states {
		SILVER_OFF: silver-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <297>;
			exit-latency-us = <324>;
			min-residency-us = <1110>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		SILVER_CLUSTER_D3: silver-cluster-d3 { /* D3 */
			compatible = "domain-idle-state";
			idle-state-name = "pwr-l2-pc";
			entry-latency-us = <800>;
			exit-latency-us = <2118>;
			min-residency-us = <7376>;
			arm,psci-suspend-param = <0x41000043>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};
		};

		CPU0: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			cpu-idle-states = <&SILVER_OFF>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			next-level-cache = <&L2_1>;
			#cooling-cells = <2>;
			L2_1: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      /* A53 L2 dump not supported */
			      qcom,dump-size = <0x0>;
			};

			L1_I_100: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_100: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU1: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			cpu-idle-states = <&SILVER_OFF>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			next-level-cache = <&L2_1>;
			#cooling-cells = <2>;
			L1_I_101: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_101: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU2: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x102>;
			cpu-idle-states = <&SILVER_OFF>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			next-level-cache = <&L2_1>;
			#cooling-cells = <2>;
			L1_I_102: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_102: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU3: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x103>;
			cpu-idle-states = <&SILVER_OFF>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			next-level-cache = <&L2_1>;
			#cooling-cells = <2>;
			L1_I_103: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_103: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};
	};

};