259 lines
8.8 KiB
Text
259 lines
8.8 KiB
Text
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#include <dt-bindings/clock/qcom,gcc-sa410m.h>
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#include <dt-bindings/phy/qcom,usb3-11nm-qmp-combo.h>
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&soc {
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/* Primary USB port related controller */
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usb0: ssusb@4e00000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x4e00000 0x100000>;
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reg-names = "core_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event_irq", "ss_phy_irq",
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"hs_phy_irq";
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USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB3_PRIM_CLKREF_EN>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"xo", "sleep_clk", "utmi_clk";
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <133333333>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
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interconnects = <&sys_noc MASTER_USB3 &bimc_noc SLAVE_EBI_CH0>,
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<&sys_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>,
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<&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>;
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dwc3@4e00000 {
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compatible = "snps,dwc3";
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reg = <0x4e00000 0xe000>;
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iommus = <&apps_smmu 0x120 0x0>;
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qcom,iommu-dma = "bypass";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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usb-phy = <&qusb_phy0>, <&usb_qmp_phy>;
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interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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tx-fifo-resize;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,is-utmi-l1-suspend;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis_u2_susphy_quirk;
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maximum-speed = "super-speed";
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dr_mode = "otg";
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};
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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/* Primary USB port related High Speed PHY */
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qusb_phy0: qusb@1613000 {
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compatible = "qcom,qusb2phy";
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reg = <0x01613000 0x180>,
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<0x003cb250 0x4>,
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<0x01b40258 0x4>,
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<0x01612000 0x4>;
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reg-names = "qusb_phy_base",
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"tcsr_clamp_dig_n_1p8",
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"tune2_efuse_addr",
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"eud_enable_reg";
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vdd-supply = <&pm2250_l12>;
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vdda18-supply = <&pm2250_l13>;
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vdda33-supply = <&pm2250_l21>;
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qcom,vdd-voltage-level = <0 925000 970000>;
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qcom,tune2-efuse-bit-pos = <25>;
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qcom,tune2-efuse-num-bits = <4>;
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qcom,qusb-phy-init-seq = <0xc8 0x80
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0xb3 0x84
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0x83 0x88
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0xc0 0x8c
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0x30 0x08
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0x79 0x0c
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0x21 0x10
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0x14 0x9c
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0x80 0x04
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0x9f 0x1c
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0x00 0x18>;
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phy_type = "utmi";
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qcom,phy-clk-scheme = "cmos";
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qcom,major-rev = <1>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&gcc GCC_AHB2PHY_USB_CLK>;
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clock-names = "ref_clk_src", "cfg_ahb_clk";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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};
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usb_qmp_phy: ssphy@1615000 {
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compatible = "qcom,usb-ssphy-qmp-usb3-or-dp";
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reg = <0x01615000 0x1000>,
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<0x03cb244 0x4>;
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reg-names = "qmp_phy_base",
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"vls_clamp_reg";
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vdd-supply = <&pm2250_l12>;
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core-supply = <&pm2250_l13>;
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qcom,vdd-voltage-level = <0 925000 970000>;
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qcom,core-voltage-level = <0 1800000 1800000>;
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qcom,qmp-phy-init-seq =
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/* <reg_offset, value, delay> */
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<USB3PHY_QSERDES_COM_SYSCLK_EN_SEL 0x14
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USB3PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x08
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USB3PHY_QSERDES_COM_CLK_SELECT 0x30
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USB3PHY_QSERDES_COM_SYS_CLK_CTRL 0x06
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USB3PHY_QSERDES_COM_RESETSM_CNTRL 0x00
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USB3PHY_QSERDES_COM_RESETSM_CNTRL2 0x08
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USB3PHY_QSERDES_COM_BG_TRIM 0x0f
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USB3PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x01
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USB3PHY_QSERDES_COM_HSCLK_SEL 0x00
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USB3PHY_QSERDES_COM_DEC_START_MODE0 0x82
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USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55
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USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x55
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USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x03
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USB3PHY_QSERDES_COM_CP_CTRL_MODE0 0x0b
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USB3PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x16
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USB3PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x28
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USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x80
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USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00
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USB3PHY_QSERDES_COM_CORECLK_DIV 0x0a
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USB3PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x15
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USB3PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x34
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USB3PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00
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USB3PHY_QSERDES_COM_LOCK_CMP_EN 0x00
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USB3PHY_QSERDES_COM_CORE_CLK_EN 0x00
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USB3PHY_QSERDES_COM_LOCK_CMP_CFG 0x00
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USB3PHY_QSERDES_COM_VCO_TUNE_MAP 0x00
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USB3PHY_QSERDES_COM_BG_TIMER 0x0a
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USB3PHY_QSERDES_COM_SSC_EN_CENTER 0x01
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USB3PHY_QSERDES_COM_SSC_PER1 0x31
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USB3PHY_QSERDES_COM_SSC_PER2 0x01
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USB3PHY_QSERDES_COM_SSC_ADJ_PER1 0x00
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USB3PHY_QSERDES_COM_SSC_ADJ_PER2 0x00
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USB3PHY_QSERDES_COM_SSC_STEP_SIZE1 0xde
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USB3PHY_QSERDES_COM_SSC_STEP_SIZE2 0x07
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USB3PHY_QSERDES_COM_PLL_IVCO 0x0f
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USB3PHY_QSERDES_COM_CMN_CONFIG 0x06
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USB3PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x80
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USB3PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x01
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USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0b
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USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0b
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USB3PHY_QSERDES_RXA_UCDR_PI_CONTROLS 0x00
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USB3PHY_QSERDES_RXB_UCDR_PI_CONTROLS 0x00
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USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x00
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USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x00
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USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x00
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USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x00
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USB3PHY_QSERDES_RXA_UCDR_FO_GAIN 0x0a
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USB3PHY_QSERDES_RXB_UCDR_FO_GAIN 0x0a
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USB3PHY_QSERDES_RXA_UCDR_SO_GAIN 0x06
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USB3PHY_QSERDES_RXB_UCDR_SO_GAIN 0x06
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USB3PHY_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x75
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USB3PHY_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x75
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USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x02
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USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x02
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USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4e
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USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4e
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USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x18
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USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18
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USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77
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USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77
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USB3PHY_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80
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USB3PHY_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80
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USB3PHY_QSERDES_RXA_VGA_CAL_CNTRL2 0x0a
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USB3PHY_QSERDES_RXB_VGA_CAL_CNTRL2 0x0a
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USB3PHY_QSERDES_RXA_SIGDET_CNTRL 0x03
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USB3PHY_QSERDES_RXB_SIGDET_CNTRL 0x03
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USB3PHY_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x16
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USB3PHY_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x16
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USB3PHY_QSERDES_RXA_SIGDET_ENABLES 0x00
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USB3PHY_QSERDES_RXB_SIGDET_ENABLES 0x00
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USB3PHY_QSERDES_RXA_RX_MODE_00 0x00
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USB3PHY_QSERDES_RXB_RX_MODE_00 0x00
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USB3PHY_QSERDES_TXA_HIGHZ_DRVR_EN 0x10
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USB3PHY_QSERDES_TXB_HIGHZ_DRVR_EN 0x10
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USB3PHY_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
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USB3PHY_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
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USB3PHY_QSERDES_TXA_LANE_MODE_1 0xc6
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USB3PHY_QSERDES_TXB_LANE_MODE_1 0xc6
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USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x00
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USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x00
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USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x00
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USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x00
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USB3PHY_PCS_TXMGN_V0 0x9f
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USB3PHY_PCS_TXDEEMPH_M6DB_V0 0x17
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USB3PHY_PCS_TXDEEMPH_M3P5DB_V0 0x0f
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USB3PHY_PCS_FLL_CNTRL2 0x83
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USB3PHY_PCS_FLL_CNTRL1 0x02
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USB3PHY_PCS_FLL_CNT_VAL_L 0x09
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USB3PHY_PCS_FLL_CNT_VAL_H_TOL 0xa2
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USB3PHY_PCS_FLL_MAN_CODE 0x85
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USB3PHY_PCS_LOCK_DETECT_CONFIG1 0xd1
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USB3PHY_PCS_LOCK_DETECT_CONFIG2 0x1f
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USB3PHY_PCS_LOCK_DETECT_CONFIG3 0x47
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USB3PHY_PCS_RXEQTRAINING_WAIT_TIME 0x75
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USB3PHY_PCS_RXEQTRAINING_RUN_TIME 0x13
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USB3PHY_PCS_LFPS_TX_ECSTART_EQTLOCK 0x86
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USB3PHY_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x04
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USB3PHY_PCS_TSYNC_RSYNC_TIME 0x44
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USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7
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USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
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USB3PHY_PCS_RCVR_DTCT_DLY_U3_L 0x40
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USB3PHY_PCS_RCVR_DTCT_DLY_U3_H 0x00
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USB3PHY_PCS_RX_SIGDET_LVL 0x88>;
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qcom,qmp-phy-reg-offset =
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<0xd74 /* USB3_PHY_PCS_STATUS */
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0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */
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0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */
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0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */
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0xc00 /* USB3_PHY_SW_RESET */
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0xc08 /* USB3_PHY_START */
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0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */
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clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
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<&gcc GCC_AHB2PHY_USB_CLK>;
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clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
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"ref_clk", "cfg_ahb_clk";
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resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
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<&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
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reset-names = "phy_reset", "phy_phy_reset";
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};
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};
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