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Rtwo/kernel/motorola/sm8550-devicetrees/qcom/sa8195-qupv3.dtsi

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initial android 16 commit
2025-09-30 20:22:48 -04:00
&soc {
/* QUPv3 West Instances
* West 0 : SE 0
* West 1 : SE 1
* West 2 : SE 2
* West 3 : SE 3
* West 4 : SE 4
* West 5 : SE 5
* West 6 : SE 6
* West 7 : SE 7
*
* QUPv3 East0 and East1 Instances
* East1 0 : SE 8
* East1 1 : SE 9
* East1 2 : SE 10
* East1 3 : SE 11
* East1 4 : SE 12
* East1 5 : SE 16
* East0 0 : SE 17
* East0 1 : SE 18
* East0 2 : SE 19
* East0 3 : SE 13
* East0 4 : SE 14
* East0 5 : SE 15
*/
/*GPI Instance */
gpi_dma0: qcom,gpi-dma@800000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0x800000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x4d6 0x0>;
qcom,max-num-gpii = <13>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0xfa>;
qcom,ev-factor = <2>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
qcom,gpi-ee-offset = <0x10000>;
dma-coherent;
status = "disabled";
};
/* QUPv3_0 wrapper instance */
qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x8c0000 0x6000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
iommus = <&apps_smmu 0x4c3 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok";
qupv3_se0_i2c: i2c@880000 {
compatible = "qcom,i2c-geni";
reg = <0x880000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_i2c_active>;
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
status = "disabled";
};
qupv3_se0_spi: spi@880000 {
compatible = "qcom,spi-geni";
reg = <0x880000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_spi_active>;
pinctrl-1 = <&qupv3_se0_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se1_i2c: i2c@884000 {
compatible = "qcom,i2c-geni";
reg = <0x884000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_i2c_active>;
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
status = "disabled";
};
qupv3_se1_spi: spi@884000 {
compatible = "qcom,spi-geni";
reg = <0x884000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_spi_active>;
pinctrl-1 = <&qupv3_se1_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se2_i2c: i2c@888000 {
compatible = "qcom,i2c-geni";
reg = <0x888000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_i2c_active>;
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
status = "disabled";
};
qupv3_se2_spi: spi@888000 {
compatible = "qcom,spi-geni";
reg = <0x888000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_spi_active>;
pinctrl-1 = <&qupv3_se2_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se3_i2c: i2c@88c000 {
compatible = "qcom,i2c-geni";
reg = <0x88c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_i2c_active>;
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
status = "disabled";
};
qupv3_se3_spi: spi@88c000 {
compatible = "qcom,spi-geni";
reg = <0x88c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_spi_active>;
pinctrl-1 = <&qupv3_se3_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se4_i2c: i2c@890000 {
compatible = "qcom,i2c-geni";
reg = <0x890000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_i2c_active>;
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
status = "disabled";
};
qupv3_se4_spi: spi@890000 {
compatible = "qcom,spi-geni";
reg = <0x890000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_spi_active>;
pinctrl-1 = <&qupv3_se4_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
/* HS UART Instance */
qupv3_se4_4uart: qcom,qup_uart@890000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0x890000 0x4000>;
reg-names = "se_phys";
interrupts-extended = <&intc GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "active", "sleep", "shutdown";
pinctrl-0 = <&qupv3_se4_default_ctsrtsrx>,
<&qupv3_se4_default_tx>;
pinctrl-1 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>,
<&qupv3_se4_tx>;
pinctrl-2 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>,
<&qupv3_se4_tx>;
pinctrl-3 = <&qupv3_se4_default_ctsrtsrx>,<&qupv3_se4_default_tx>;
qcom,wakeup-byte = <0xFD>;
status = "disabled";
};
qupv3_se5_i2c: i2c@894000 {
compatible = "qcom,i2c-geni";
reg = <0x894000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_i2c_active>;
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
status = "disabled";
};
qupv3_se5_spi: spi@894000 {
compatible = "qcom,spi-geni";
reg = <0x894000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_spi_active>;
pinctrl-1 = <&qupv3_se5_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se6_i2c: i2c@898000 {
compatible = "qcom,i2c-geni";
reg = <0x898000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_i2c_active>;
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
status = "disabled";
};
qupv3_se6_spi: spi@898000 {
compatible = "qcom,spi-geni";
reg = <0x898000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_spi_active>;
pinctrl-1 = <&qupv3_se6_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se7_i2c: i2c@89c000 {
compatible = "qcom,i2c-geni";
reg = <0x89c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_i2c_active>;
pinctrl-1 = <&qupv3_se7_i2c_sleep>;
status = "disabled";
};
qupv3_se7_spi: spi@89c000 {
compatible = "qcom,spi-geni";
reg = <0x89c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_spi_active>;
pinctrl-1 = <&qupv3_se7_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
};
/* GPI Instance */
gpi_dma1: qcom,gpi-dma@a00000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0xa00000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x616 0x0>;
qcom,max-num-gpii = <13>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0xfa>;
qcom,ev-factor = <2>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
qcom,gpi-ee-offset = <0x10000>;
dma-coherent;
status = "disabled";
};
/* QUPv3_1 wrapper instance */
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0xac0000 0x6000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0x603 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok";
qupv3_se8_i2c: i2c@a80000 {
compatible = "qcom,i2c-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_i2c_active>;
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
status = "disabled";
};
qupv3_se8_spi: spi@a80000 {
compatible = "qcom,spi-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_spi_active>;
pinctrl-1 = <&qupv3_se8_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se9_i2c: i2c@a84000 {
compatible = "qcom,i2c-geni";
reg = <0xa84000 0x4000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_i2c_active>;
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
status = "disabled";
};
qupv3_se9_spi: spi@a84000 {
compatible = "qcom,spi-geni";
reg = <0xa84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_spi_active>;
pinctrl-1 = <&qupv3_se9_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se10_i2c: i2c@a88000 {
compatible = "qcom,i2c-geni";
reg = <0xa88000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se10_i2c_active>;
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
status = "disabled";
};
qupv3_se10_spi: spi@a88000 {
compatible = "qcom,spi-geni";
reg = <0xa88000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se10_spi_active>;
pinctrl-1 = <&qupv3_se10_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se10_2uart: qcom,qup_uart@a88000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0xa88000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se10_2uart_active>;
pinctrl-1 = <&qupv3_se10_2uart_sleep>;
status = "disabled";
};
qupv3_se11_i2c: i2c@a8c000 {
compatible = "qcom,i2c-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se11_i2c_active>;
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
status = "disabled";
};
qupv3_se11_spi: spi@a8c000 {
compatible = "qcom,spi-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se11_spi_active>;
pinctrl-1 = <&qupv3_se11_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se12_i2c: i2c@a90000 {
compatible = "qcom,i2c-geni";
reg = <0xa90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se12_i2c_active>;
pinctrl-1 = <&qupv3_se12_i2c_sleep>;
status = "disabled";
};
qupv3_se12_spi: spi@a90000 {
compatible = "qcom,spi-geni";
reg = <0xa90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se12_spi_active>;
pinctrl-1 = <&qupv3_se12_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
/* Debug UART Instance for CDP/MTP platform */
qupv3_se12_2uart: qcom,qup_uart@a90000 {
compatible = "qcom,geni-debug-uart";
reg = <0xa90000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se12_2uart_active>;
pinctrl-1 = <&qupv3_se12_2uart_sleep>;
status = "disabled";
};
qupv3_se13_i2c: i2c@a94000 {
compatible = "qcom,i2c-geni";
reg = <0xa94000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_i2c_active>;
pinctrl-1 = <&qupv3_se13_i2c_sleep>;
status = "disabled";
};
qupv3_se13_spi: spi@a94000 {
compatible = "qcom,spi-geni";
reg = <0xa94000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_spi_active>;
pinctrl-1 = <&qupv3_se13_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se13_2uart: qcom,qup_uart@a94000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0xa94000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_2uart_active>;
pinctrl-1 = <&qupv3_se13_2uart_sleep>;
status = "disabled";
};
};
/* GPI Instance */
gpi_dma2: qcom,gpi-dma@c00000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0xc00000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x7b6 0x0>;
qcom,max-num-gpii = <13>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0xfa>;
qcom,ev-factor = <2>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
qcom,gpi-ee-offset = <0x10000>;
dma-coherent;
status = "disabled";
};
/* QUPv3_2 wrapper instance */
qupv3_2: qcom,qupv3_2_geni_se@cc0000 {
compatible = "qcom,geni-se-qup";
reg = <0xcc0000 0x6000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
iommus = <&apps_smmu 0x7a3 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok";
qupv3_se14_i2c: i2c@c80000 {
compatible = "qcom,i2c-geni";
reg = <0xc80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se14_i2c_active>;
pinctrl-1 = <&qupv3_se14_i2c_sleep>;
status = "disabled";
};
qupv3_se14_spi: spi@c80000 {
compatible = "qcom,spi-geni";
reg = <0xc80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se14_spi_active>;
pinctrl-1 = <&qupv3_se14_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se15_i2c: i2c@c84000 {
compatible = "qcom,i2c-geni";
reg = <0xc84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se15_i2c_active>;
pinctrl-1 = <&qupv3_se15_i2c_sleep>;
status = "disabled";
};
qupv3_se15_spi: spi@c84000 {
compatible = "qcom,spi-geni";
reg = <0xc84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se15_spi_active>;
pinctrl-1 = <&qupv3_se15_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se16_i2c: i2c@c88000 {
compatible = "qcom,i2c-geni";
reg = <0xc88000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se16_i2c_active>;
pinctrl-1 = <&qupv3_se16_i2c_sleep>;
status = "disabled";
};
qupv3_se16_spi: spi@c88000 {
compatible = "qcom,spi-geni";
reg = <0xc88000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se16_spi_active>;
pinctrl-1 = <&qupv3_se16_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se17_i2c: i2c@c8c000 {
compatible = "qcom,i2c-geni";
reg = <0xc8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se17_i2c_active>;
pinctrl-1 = <&qupv3_se17_i2c_sleep>;
status = "disabled";
};
qupv3_se17_spi: spi@c8c000 {
compatible = "qcom,spi-geni";
reg = <0xc8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se17_spi_active>;
pinctrl-1 = <&qupv3_se17_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
/* HS UART Instance */
qupv3_se17_4uart: qcom,qup_uart@c8c000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0xc8c000 0x4000>;
reg-names = "se_phys";
interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 46 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "active", "sleep", "shutdown";
pinctrl-0 = <&qupv3_se17_default_ctsrtsrx>,
<&qupv3_se17_default_tx>;
pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
<&qupv3_se17_tx>;
pinctrl-2 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
<&qupv3_se17_tx>;
pinctrl-3 = <&qupv3_se17_default_ctsrtsrx>,<&qupv3_se17_default_tx>;
qcom,wakeup-byte = <0xFD>;
status = "disabled";
};
qupv3_se18_i2c: i2c@c90000 {
compatible = "qcom,i2c-geni";
reg = <0xc90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se18_i2c_active>;
pinctrl-1 = <&qupv3_se18_i2c_sleep>;
status = "disabled";
};
qupv3_se18_spi: spi@c90000 {
compatible = "qcom,spi-geni";
reg = <0xc90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se18_spi_active>;
pinctrl-1 = <&qupv3_se18_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se19_i2c: i2c@c94000 {
compatible = "qcom,i2c-geni";
reg = <0xc94000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se19_i2c_active>;
pinctrl-1 = <&qupv3_se19_i2c_sleep>;
status = "disabled";
};
qupv3_se19_spi: spi@c94000 {
compatible = "qcom,spi-geni";
reg = <0xc94000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se19_spi_active>;
pinctrl-1 = <&qupv3_se19_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
};
};
Reference in a new issue Copy permalink