578 lines
20 KiB
Text
578 lines
20 KiB
Text
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/phy/qcom,qcs605-qmp-usb3.h>
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&soc {
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/* Primary USB port related DWC3 controller */
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x0a600000 0xf8c00>,
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<0x088ee000 0x400>;
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reg-names = "core_base", "ahb2phy_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <0 489 IRQ_TYPE_LEVEL_HIGH>,
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<0 130 IRQ_TYPE_LEVEL_HIGH>,
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<0 486 IRQ_TYPE_LEVEL_HIGH>,
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<0 488 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"ss_phy_irq", "dm_hs_phy_irq";
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USB3_GDSC-supply = <&usb30_prim_gdsc>;
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qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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qcom,use-pdc-interrupts;
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qcom,pm-qos-latency = <44>;
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_USB3_PRIM_CLKREF_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo";
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qcom,core-clk-rate = <133333333>;
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qcom,core-clk-rate-hs = <66666667>;
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0x0a600000 0xcd00>;
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iommus = <&apps_smmu 0x740 0x0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>;
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tx-fifo-resize;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3_lpm_capable;
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usb-core-id = <0>;
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maximum-speed = "super-speed";
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dr_mode = "otg";
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usb-role-switch;
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};
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qcom,usbbam@a704000 {
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compatible = "qcom,usb-bam-msm";
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reg = <0xa704000 0x17000>;
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interrupts = <0 132 IRQ_TYPE_LEVEL_HIGH>;
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qcom,bam-type = <0>;
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qcom,usb-bam-fifo-baseaddr = <0x146bb000>;
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qcom,usb-bam-num-pipes = <8>;
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qcom,ignore-core-reset-ack;
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qcom,disable-clk-gating;
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qcom,usb-bam-override-threshold = <0x4001>;
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qcom,usb-bam-max-mbps-highspeed = <400>;
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qcom,usb-bam-max-mbps-superspeed = <3600>;
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qcom,reset-bam-on-connect;
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qcom,pipe0 {
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label = "ssusb-qdss-in-0";
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qcom,usb-bam-mem-type = <2>;
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qcom,dir = <1>;
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qcom,pipe-num = <0>;
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qcom,peer-bam = <0>;
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qcom,peer-bam-physical-address = <0x6064000>;
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qcom,src-bam-pipe-index = <0>;
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qcom,dst-bam-pipe-index = <0>;
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qcom,data-fifo-offset = <0x0>;
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qcom,data-fifo-size = <0x1800>;
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qcom,descriptor-fifo-offset = <0x1800>;
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qcom,descriptor-fifo-size = <0x800>;
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};
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};
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};
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/* Primary USB port related QUSB2 PHY */
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qusb_phy0: qusb@88e2000 {
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compatible = "qcom,qusb2phy-v2";
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reg = <0x088e2000 0x400>,
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<0x007801e8 0x4>,
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<0x088e7014 0x4>;
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reg-names = "qusb_phy_base", "efuse_addr",
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"refgen_north_bg_reg_addr";
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qcom,efuse-bit-pos = <25>;
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qcom,efuse-num-bits = <3>;
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vdd-supply = <&pm8998_l1>;
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vdda18-supply = <&pm8998_l12>;
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vdda33-supply = <&pm8998_l24>;
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qcom,override-bias-ctrl2;
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qcom,vdd-voltage-level = <0 880000 880000>;
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qcom,qusb-phy-reg-offset =
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<0x240 /* QUSB2PHY_PORT_TUNE1 */
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0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */
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0x210 /* QUSB2PHY_PWR_CTRL1 */
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0x230 /* QUSB2PHY_INTR_CTRL */
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0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */
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0x254 /* QUSB2PHY_TEST1 */
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0x198 /* PLL_BIAS_CONTROL_2 */
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0x27c /* QUSB2PHY_DEBUG_CTRL1 */
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0x280 /* QUSB2PHY_DEBUG_CTRL2 */
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0x284 /* QUSB2PHY_DEBUG_CTRL3 */
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0x288 /* QUSB2PHY_DEBUG_CTRL4 */
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0x2a0>; /* QUSB2PHY_STAT5 */
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qcom,qusb-phy-init-seq =
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/* <value reg_offset> */
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<0x23 0x210 /* PWR_CTRL1 */
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0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
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0x7c 0x18c /* PLL_CLOCK_INVERTERS */
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0x80 0x2c /* PLL_CMODE */
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0x0a 0x184 /* PLL_LOCK_DELAY */
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0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
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0x40 0x194 /* PLL_BIAS_CONTROL_1 */
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0x20 0x198 /* PLL_BIAS_CONTROL_2 */
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0x21 0x214 /* PWR_CTRL2 */
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0x00 0x220 /* IMP_CTRL1 */
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0x58 0x224 /* IMP_CTRL2 */
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0x30 0x240 /* TUNE1 */
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0x29 0x244 /* TUNE2 */
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0xca 0x248 /* TUNE3 */
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0x04 0x24c /* TUNE4 */
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0x03 0x250 /* TUNE5 */
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0x00 0x23c /* CHG_CTRL2 */
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0x22 0x210>; /* PWR_CTRL1 */
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phy_type= "utmi";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
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clock-names = "ref_clk_src", "cfg_ahb_clk";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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};
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/* Primary USB port related QMP USB DP Combo PHY */
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usb_qmp_dp_phy: ssphy@88e8000 {
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compatible = "qcom,usb-ssphy-qmp-dp-combo";
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reg = <0x88e8000 0x3000>;
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reg-names = "qmp_phy_base";
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vdd-supply = <&pm8998_l1>;
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core-supply = <&pm8998_l26>;
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qcom,vdd-voltage-level = <0 880000 880000>;
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qcom,vbus-valid-override;
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qcom,qmp-phy-init-seq =
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/* <reg_offset, value, delay> */
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<USB3_DP_QSERDES_COM_CLK_ENABLE1 0x07
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USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x14
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x08
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USB3_DP_QSERDES_COM_VCO_TUNE_TIMER1 0x30
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USB3_DP_QSERDES_COM_POST_DIV 0x02
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USB3_DP_QSERDES_COM_PLL_CNTRL 0x08
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USB3_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL 0x16
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USB3_DP_QSERDES_COM_PLL_ANALOG 0x01
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USB3_DP_QSERDES_COM_VCO_TUNE_TIMER2 0x80
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USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x82
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USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0xab
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USB3_DP_QSERDES_COM_DEC_START_MODE0 0xea
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USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x02
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USB3_DP_QSERDES_COM_CMN_IPTRIM 0x06
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USB3_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x16
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USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE1 0x36
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USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x00
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USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x3f
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USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x01
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USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0xc9
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USB3_DP_QSERDES_COM_RESTRIM_CODE_STATUS 0x0a
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USB3_DP_QSERDES_COM_RESETSM_CNTRL2 0x00
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USB3_DP_QSERDES_COM_RESETSM_CNTRL 0x34
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USB3_DP_QSERDES_COM_CML_SYSCLK_SEL 0x15
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USB3_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x04
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USB3_DP_QSERDES_COM_CLK_SELECT 0x00
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USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x00
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USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00
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USB3_DP_QSERDES_COM_POST_DIV_MUX 0x0a
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USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
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USB3_DP_QSERDES_COM_SSC_PER1 0x31
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USB3_DP_QSERDES_COM_SSC_PER2 0x01
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USB3_DP_QSERDES_COM_SSC_ADJ_PER1 0x00
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USB3_DP_QSERDES_COM_SSC_ADJ_PER2 0x00
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x85
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
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USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0b
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USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x0f
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USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x4e
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USB3_DP_QSERDES_RXA_GM_CAL 0x18
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USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x77
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USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x80
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USB3_DP_QSERDES_RXA_RX_IDAC_ACCUMULATOR 0x03
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USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_MSB 0x16
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USB3_DP_QSERDES_RXA_RX_PWM_GEAR2_TIMEOUT_COUNT 0x05
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USB3_DP_QSERDES_RXA_DFE_4 0x03
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USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0b
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USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x0f
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USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x4e
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USB3_DP_QSERDES_RXB_GM_CAL 0x18
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USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x77
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USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x80
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USB3_DP_QSERDES_RXB_RX_IDAC_ACCUMULATOR 0x03
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USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_MSB 0x16
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USB3_DP_QSERDES_RXB_RX_PWM_GEAR2_TIMEOUT_COUNT 0x05
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USB3_DP_QSERDES_RXB_DFE_4 0x03
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USB3_DP_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN 0x10
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USB3_DP_QSERDES_TXA_PRBS_SEED2 0x12
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USB3_DP_QSERDES_TXA_LANE_MODE_3 0x16
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USB3_DP_QSERDES_TXA_PERL_LENGTH2 0x09
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USB3_DP_QSERDES_TXA_PERL_LENGTH1 0x06
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USB3_DP_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN 0x10
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USB3_DP_QSERDES_TXB_PRBS_SEED2 0x12
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USB3_DP_QSERDES_TXB_LANE_MODE_3 0x16
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USB3_DP_QSERDES_TXB_PERL_LENGTH2 0x09
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USB3_DP_QSERDES_TXB_PERL_LENGTH1 0x06
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USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x83
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USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x09
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USB3_DP_PCS_LOCK_DETECT_CONFIG4 0xa2
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USB3_DP_PCS_LOCK_DETECT_CONFIG5 0x40
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USB3_DP_PCS_LOCK_DETECT_CONFIG1 0x02
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USB3_DP_PCS_INSIG_MX_CTRL8 0xd1
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USB3_DP_PCS_OUTSIG_SW_CTRL1 0x1f
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USB3_DP_PCS_OUTSIG_MX_CTRL1 0x47
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USB3_DP_PCS_INSIG_SW_CTRL8 0x1b
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USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x75
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USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x75
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USB3_DP_PCS_RX_DCC_CAL_CONFIG 0xba
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USB3_DP_PCS_REVISION_ID2 0x9f
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USB3_DP_PCS_REVISION_ID3 0x9f
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USB3_DP_PCS_PCS_STATUS1 0xb7
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USB3_DP_PCS_PCS_STATUS2 0x4e
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USB3_DP_PCS_PCS_STATUS3 0x65
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USB3_DP_PCS_PCS_STATUS4 0x6b
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USB3_DP_PCS_PCS_STATUS5 0x15
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USB3_DP_PCS_PCS_STATUS6 0x0d
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USB3_DP_PCS_PCS_STATUS7 0x15
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USB3_DP_PCS_DEBUG_BUS_0_STATUS 0x0d
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USB3_DP_PCS_DEBUG_BUS_1_STATUS 0x15
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USB3_DP_PCS_DEBUG_BUS_2_STATUS 0x0d
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USB3_DP_PCS_DEBUG_BUS_3_STATUS 0x15
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USB3_DP_PCS_POWER_DOWN_CONTROL 0x1d
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USB3_DP_PCS_START_CONTROL 0x15
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USB3_DP_PCS_INSIG_SW_CTRL1 0x0d
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USB3_DP_PCS_INSIG_SW_CTRL2 0x15
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USB3_DP_PCS_INSIG_SW_CTRL3 0x0d
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USB3PHY_PCS_REFGEN_REQ_CONFIG1 0x21
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USB3PHY_PCS_REFGEN_REQ_CONFIG2 0x60
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USB3_DP_PCS_INSIG_SW_CTRL6 0x02
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USB3_DP_PCS_FLL_CNT_VAL_L 0x04
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USB3_DP_PCS_CLAMP_ENABLE 0x44
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USB3_DP_PCS_INSIG_MX_CTRL3 0xe7
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||
|
|
USB3_DP_PCS_INSIG_MX_CTRL4 0x03
|
||
|
|
USB3_DP_PCS_INSIG_MX_CTRL5 0x40
|
||
|
|
USB3_DP_PCS_INSIG_MX_CTRL7 0x00
|
||
|
|
USB3_DP_PCS_TEST_CONTROL4 0x75
|
||
|
|
USB3_DP_PCS_TEST_CONTROL2 0x86
|
||
|
|
USB3_DP_PCS_TEST_CONTROL5 0x13
|
||
|
|
USB3_DP_PCS_TEST_CONTROL1 0x04>;
|
||
|
|
|
||
|
|
qcom,qmp-phy-reg-offset =
|
||
|
|
<0x1d74 /* USB3_DP_PCS_PCS_STATUS */
|
||
|
|
0x1cd8 /* USB3_DP_PCS_AUTONOMOUS_MODE_CTRL */
|
||
|
|
0x1cdc /* USB3_DP_PCS_LFPS_RXTERM_IRQ_CLEAR */
|
||
|
|
0x1c04 /* USB3_DP_PCS_POWER_DOWN_CONTROL */
|
||
|
|
0x1c00 /* USB3_DP_PCS_SW_RESET */
|
||
|
|
0x1c08 /* USB3_DP_PCS_START_CONTROL */
|
||
|
|
0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
|
||
|
|
0x0008 /* USB3_DP_COM_POWER_DOWN_CTRL */
|
||
|
|
0x0004 /* USB3_DP_COM_SW_RESET */
|
||
|
|
0x001c /* USB3_DP_COM_RESET_OVRD_CTRL */
|
||
|
|
0x0000 /* USB3_DP_COM_PHY_MODE_CTRL */
|
||
|
|
0x0010 /* USB3_DP_COM_TYPEC_CTRL */
|
||
|
|
0x1a0c>; /* USB3_DP_PCS_MISC_CLAMP_ENABLE */
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
|
||
|
|
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
||
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
||
|
|
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
|
||
|
|
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
|
||
|
|
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
|
||
|
|
|
||
|
|
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
|
||
|
|
"ref_clk", "com_aux_clk", "cfg_ahb_clk";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
|
||
|
|
<&gcc GCC_USB3_PHY_PRIM_BCR>;
|
||
|
|
reset-names = "global_phy_reset", "phy_reset";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb_audio_qmi_dev {
|
||
|
|
compatible = "qcom,usb-audio-qmi-dev";
|
||
|
|
iommus = <&apps_smmu 0x182c 0x0>;
|
||
|
|
qcom,usb-audio-stream-id = <0xc>;
|
||
|
|
qcom,usb-audio-intr-num = <2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
usb_nop_phy: usb_nop_phy {
|
||
|
|
compatible = "usb-nop-xceiv";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Secondary USB port related DWC3 controller */
|
||
|
|
usb1: ssusb@a800000 {
|
||
|
|
compatible = "qcom,dwc-usb3-msm";
|
||
|
|
reg = <0x0a800000 0xf8c00>,
|
||
|
|
<0x088ee000 0x400>;
|
||
|
|
reg-names = "core_base", "ahb2phy_base";
|
||
|
|
iommus = <&apps_smmu 0x760 0x0>;
|
||
|
|
qcom,smmu-s1-bypass;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
interrupts = <0 491 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<0 135 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<0 487 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<0 490 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
|
||
|
|
"ss_phy_irq", "dm_hs_phy_irq";
|
||
|
|
|
||
|
|
USB3_GDSC-supply = <&usb30_sec_gdsc>;
|
||
|
|
qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
|
||
|
|
qcom,use-pdc-interrupts;
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
|
||
|
|
<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
||
|
|
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
||
|
|
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
||
|
|
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
|
||
|
|
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
|
||
|
|
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
|
||
|
|
|
||
|
|
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||
|
|
"utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo";
|
||
|
|
|
||
|
|
qcom,core-clk-rate = <133333333>;
|
||
|
|
qcom,core-clk-rate-hs = <66666667>;
|
||
|
|
|
||
|
|
resets = <&gcc GCC_USB30_SEC_BCR>;
|
||
|
|
reset-names = "core_reset";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
dwc3@a800000 {
|
||
|
|
compatible = "snps,dwc3";
|
||
|
|
reg = <0x0a800000 0xcd00>;
|
||
|
|
interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
usb-phy = <&qusb_phy1>, <&usb_qmp_phy>;
|
||
|
|
tx-fifo-resize;
|
||
|
|
linux,sysdev_is_parent;
|
||
|
|
snps,disable-clk-gating;
|
||
|
|
snps,has-lpm-erratum;
|
||
|
|
snps,hird-threshold = /bits/ 8 <0x10>;
|
||
|
|
snps,usb3_lpm_capable;
|
||
|
|
usb-core-id = <1>;
|
||
|
|
dr_mode = "host";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Secondary USB port related QUSB2 PHY */
|
||
|
|
qusb_phy1: qusb@88e3000 {
|
||
|
|
compatible = "qcom,qusb2phy-v2";
|
||
|
|
reg = <0x088e3000 0x400>,
|
||
|
|
<0x088e7014 0x4>;
|
||
|
|
reg-names = "qusb_phy_base",
|
||
|
|
"refgen_north_bg_reg_addr";
|
||
|
|
|
||
|
|
vdd-supply = <&pm8998_l1>;
|
||
|
|
vdda18-supply = <&pm8998_l12>;
|
||
|
|
vdda33-supply = <&pm8998_l24>;
|
||
|
|
qcom,override-bias-ctrl2;
|
||
|
|
qcom,vdd-voltage-level = <0 880000 880000>;
|
||
|
|
qcom,qusb-phy-reg-offset =
|
||
|
|
<0x240 /* QUSB2PHY_PORT_TUNE1 */
|
||
|
|
0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */
|
||
|
|
0x210 /* QUSB2PHY_PWR_CTRL1 */
|
||
|
|
0x230 /* QUSB2PHY_INTR_CTRL */
|
||
|
|
0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */
|
||
|
|
0x254 /* QUSB2PHY_TEST1 */
|
||
|
|
0x198 /* PLL_BIAS_CONTROL_2 */
|
||
|
|
0x27c /* QUSB2PHY_DEBUG_CTRL1 */
|
||
|
|
0x280 /* QUSB2PHY_DEBUG_CTRL2 */
|
||
|
|
0x2a0>; /* QUSB2PHY_STAT5 */
|
||
|
|
|
||
|
|
qcom,qusb-phy-init-seq =
|
||
|
|
/* <value reg_offset> */
|
||
|
|
<0x23 0x210 /* PWR_CTRL1 */
|
||
|
|
0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
|
||
|
|
0x7c 0x18c /* PLL_CLOCK_INVERTERS */
|
||
|
|
0x80 0x2c /* PLL_CMODE */
|
||
|
|
0x0a 0x184 /* PLL_LOCK_DELAY */
|
||
|
|
0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
|
||
|
|
0x40 0x194 /* PLL_BIAS_CONTROL_1 */
|
||
|
|
0x20 0x198 /* PLL_BIAS_CONTROL_2 */
|
||
|
|
0x21 0x214 /* PWR_CTRL2 */
|
||
|
|
0x00 0x220 /* IMP_CTRL1 */
|
||
|
|
0x58 0x224 /* IMP_CTRL2 */
|
||
|
|
0x20 0x240 /* TUNE1 */
|
||
|
|
0x29 0x244 /* TUNE2 */
|
||
|
|
0xca 0x248 /* TUNE3 */
|
||
|
|
0x04 0x24c /* TUNE4 */
|
||
|
|
0x03 0x250 /* TUNE5 */
|
||
|
|
0x00 0x23c /* CHG_CTRL2 */
|
||
|
|
0x22 0x210>; /* PWR_CTRL1 */
|
||
|
|
|
||
|
|
phy_type= "utmi";
|
||
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||
|
|
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
|
||
|
|
clock-names = "ref_clk_src", "cfg_ahb_clk";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
||
|
|
reset-names = "phy_reset";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Secondary USB port related QMP PHY */
|
||
|
|
usb_qmp_phy: ssphy@88eb000 {
|
||
|
|
compatible = "qcom,usb-ssphy-qmp-v2";
|
||
|
|
reg = <0x88eb000 0x1000>,
|
||
|
|
<0x01fcbff0 0x4>;
|
||
|
|
reg-names = "qmp_phy_base",
|
||
|
|
"vls_clamp_reg";
|
||
|
|
|
||
|
|
vdd-supply = <&pm8998_l1>;
|
||
|
|
core-supply = <&pm8998_l26>;
|
||
|
|
qcom,vdd-voltage-level = <0 880000 880000>;
|
||
|
|
qcom,vbus-valid-override;
|
||
|
|
qcom,qmp-phy-init-seq =
|
||
|
|
/* <reg_offset, value, delay> */
|
||
|
|
<0x048 0x07 0x00 /* QSERDES_COM_PLL_IVCO */
|
||
|
|
0x080 0x14 0x00 /* QSERDES_COM_SYSCLK_EN_SEL */
|
||
|
|
0x034 0x04 0x00 /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */
|
||
|
|
0x138 0x30 0x00 /* QSERDES_COM_CLK_SELECT */
|
||
|
|
0x03c 0x02 0x00 /* QSERDES_COM_SYS_CLK_CTRL */
|
||
|
|
0x08c 0x08 0x00 /* QSERDES_COM_RESETSM_CNTRL2 */
|
||
|
|
0x15c 0x06 0x00 /* QSERDES_COM_CMN_CONFIG */
|
||
|
|
0x164 0x01 0x00 /* QSERDES_COM_SVS_MODE_CLK_SEL */
|
||
|
|
0x13c 0x80 0x00 /* QSERDES_COM_HSCLK_SEL */
|
||
|
|
0x0b0 0x82 0x00 /* QSERDES_COM_DEC_START_MODE0 */
|
||
|
|
0x0b8 0xab 0x00 /* QSERDES_COM_DIV_FRAC_START1_MODE0 */
|
||
|
|
0x0bc 0xea 0x00 /* QSERDES_COM_DIV_FRAC_START2_MODE0 */
|
||
|
|
0x0c0 0x02 0x00 /* QSERDES_COM_DIV_FRAC_START3_MODE0 */
|
||
|
|
0x060 0x06 0x00 /* QSERDES_COM_CP_CTRL_MODE0 */
|
||
|
|
0x068 0x16 0x00 /* QSERDES_COM_PLL_RCTRL_MODE0 */
|
||
|
|
0x070 0x36 0x00 /* QSERDES_COM_PLL_CCTRL_MODE0 */
|
||
|
|
0x0dc 0x00 0x00 /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */
|
||
|
|
0x0d8 0x3f 0x00 /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */
|
||
|
|
0x0f8 0x01 0x00 /* QSERDES_COM_VCO_TUNE2_MODE0 */
|
||
|
|
0x0f4 0xc9 0x00 /* QSERDES_COM_VCO_TUNE1_MODE0 */
|
||
|
|
0x148 0x0a 0x00 /* QSERDES_COM_CORECLK_DIV_MODE0 */
|
||
|
|
0x0a0 0x00 0x00 /* QSERDES_COM_LOCK_CMP3_MODE0 */
|
||
|
|
0x09c 0x34 0x00 /* QSERDES_COM_LOCK_CMP2_MODE0 */
|
||
|
|
0x098 0x15 0x00 /* QSERDES_COM_LOCK_CMP1_MODE0 */
|
||
|
|
0x090 0x04 0x00 /* QSERDES_COM_LOCK_CMP_EN */
|
||
|
|
0x154 0x00 0x00 /* QSERDES_COM_CORE_CLK_EN */
|
||
|
|
0x094 0x00 0x00 /* QSERDES_COM_LOCK_CMP_CFG */
|
||
|
|
0x0f0 0x00 0x00 /* QSERDES_COM_VCO_TUNE_MAP */
|
||
|
|
0x040 0x0a 0x00 /* QSERDES_COM_SYSCLK_BUF_ENABLE */
|
||
|
|
0x0d0 0x80 0x00 /* QSERDES_COM_INTEGLOOP_INITVAL */
|
||
|
|
0x010 0x01 0x00 /* QSERDES_COM_SSC_EN_CENTER */
|
||
|
|
0x01c 0x31 0x00 /* QSERDES_COM_SSC_PER1 */
|
||
|
|
0x020 0x01 0x00 /* QSERDES_COM_SSC_PER2 */
|
||
|
|
0x014 0x00 0x00 /* QSERDES_COM_SSC_ADJ_PER1 */
|
||
|
|
0x018 0x00 0x00 /* QSERDES_COM_SSC_ADJ_PER2 */
|
||
|
|
0x024 0x85 0x00 /* QSERDES_COM_SSC_STEP_SIZE1 */
|
||
|
|
0x028 0x07 0x00 /* QSERDES_COM_SSC_STEP_SIZE2 */
|
||
|
|
0x4c0 0x0c 0x00 /* QSERDES_RX_VGA_CAL_CNTRL2 */
|
||
|
|
0x564 0x50 0x00 /* QSERDES_RX_RX_MODE_00 */
|
||
|
|
0x430 0x0b 0x00 /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */
|
||
|
|
0x4d4 0x0e 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */
|
||
|
|
0x4d8 0x4e 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */
|
||
|
|
0x4dc 0x18 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */
|
||
|
|
0x4f8 0x77 0x00 /* RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
|
||
|
|
0x4fc 0x80 0x00 /* RX_RX_OFFSET_ADAPTOR_CNTRL2 */
|
||
|
|
0x504 0x03 0x00 /* QSERDES_RX_SIGDET_CNTRL */
|
||
|
|
0x50c 0x1c 0x00 /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
|
||
|
|
0x434 0x75 0x00 /* RX_UCDR_SO_SATURATION_AND_ENABLE */
|
||
|
|
0x444 0x80 0x00 /* QSERDES_RX_UCDR_PI_CONTROLS */
|
||
|
|
0x408 0x0a 0x00 /* QSERDES_RX_UCDR_FO_GAIN */
|
||
|
|
0x40c 0x06 0x00 /* QSERDES_RX_UCDR_SO_GAIN */
|
||
|
|
0x500 0x00 0x00 /* QSERDES_RX_SIGDET_ENABLES */
|
||
|
|
0x260 0x10 0x00 /* QSERDES_TX_HIGHZ_DRVR_EN */
|
||
|
|
0x2a4 0x12 0x00 /* QSERDES_TX_RCV_DETECT_LVL_2 */
|
||
|
|
0x28c 0xc6 0x00 /* QSERDES_TX_LANE_MODE_1 */
|
||
|
|
0x248 0x06 0x00 /* TX_RES_CODE_LANE_OFFSET_RX */
|
||
|
|
0x244 0x06 0x00 /* TX_RES_CODE_LANE_OFFSET_TX */
|
||
|
|
0x8c8 0x83 0x00 /* USB3_UNI_PCS_FLL_CNTRL2 */
|
||
|
|
0x8cc 0x09 0x00 /* USB3_UNI_PCS_FLL_CNT_VAL_L */
|
||
|
|
0x8d0 0xa2 0x00 /* USB3_UNI_PCS_FLL_CNT_VAL_H_TOL */
|
||
|
|
0x8d4 0x40 0x00 /* USB3_UNI_PCS_FLL_MAN_CODE */
|
||
|
|
0x8c4 0x02 0x00 /* USB3_UNI_PCS_FLL_CNTRL1 */
|
||
|
|
0x864 0x1b 0x00 /* USB3_UNI_PCS_POWER_STATE_CONFIG2 */
|
||
|
|
0x80c 0x9f 0x00 /* USB3_UNI_PCS_TXMGN_V0 */
|
||
|
|
0x810 0x9f 0x00 /* USB3_UNI_PCS_TXMGN_V1 */
|
||
|
|
0x814 0xb5 0x00 /* USB3_UNI_PCS_TXMGN_V2 */
|
||
|
|
0x818 0x4c 0x00 /* USB3_UNI_PCS_TXMGN_V3 */
|
||
|
|
0x81c 0x64 0x00 /* USB3_UNI_PCS_TXMGN_V4 */
|
||
|
|
0x820 0x6a 0x00 /* USB3_UNI_PCS_TXMGN_LS */
|
||
|
|
0x824 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V0 */
|
||
|
|
0x828 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V0 */
|
||
|
|
0x82c 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V1 */
|
||
|
|
0x830 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V1 */
|
||
|
|
0x834 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V2 */
|
||
|
|
0x838 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V2 */
|
||
|
|
0x83c 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V3 */
|
||
|
|
0x840 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V3 */
|
||
|
|
0x844 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V4 */
|
||
|
|
0x848 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V4 */
|
||
|
|
0x84c 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_LS */
|
||
|
|
0x850 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_LS */
|
||
|
|
0x85c 0x02 0x00 /* USB3_UNI_PCS_RATE_SLEW_CNTRL */
|
||
|
|
0x8a0 0x04 0x00 /* PCS_PWRUP_RESET_DLY_TIME_AUXCLK */
|
||
|
|
0x88c 0x44 0x00 /* USB3_UNI_PCS_TSYNC_RSYNC_TIME */
|
||
|
|
0x880 0xd1 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG1 */
|
||
|
|
0x884 0x1f 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG2 */
|
||
|
|
0x888 0x47 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG3 */
|
||
|
|
0x870 0xe7 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L */
|
||
|
|
0x874 0x03 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H */
|
||
|
|
0x878 0x40 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_U3_L */
|
||
|
|
0x87c 0x00 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_U3_H */
|
||
|
|
0x9d8 0xba 0x00 /* USB3_UNI_PCS_RX_SIGDET_LVL */
|
||
|
|
0x8b8 0x75 0x00 /* RXEQTRAINING_WAIT_TIME */
|
||
|
|
0x8b0 0x86 0x00 /* PCS_LFPS_TX_ECSTART_EQTLOCK */
|
||
|
|
0x8bc 0x13 0x00 /* PCS_RXEQTRAINING_RUN_TIME */
|
||
|
|
0xa0c 0x21 0x00 /* USB3_UNI_PCS_REFGEN_REQ_CONFIG1 */
|
||
|
|
0xa10 0x60 0x00 /* USB3_UNI_PCS_REFGEN_REQ_CONFIG2 */
|
||
|
|
0xffffffff 0xffffffff 0x00>;
|
||
|
|
|
||
|
|
qcom,qmp-phy-reg-offset =
|
||
|
|
<0x974 /* USB3_UNI_PCS_PCS_STATUS */
|
||
|
|
0x8d8 /* USB3_UNI_PCS_AUTONOMOUS_MODE_CTRL */
|
||
|
|
0x8dc /* USB3_UNI_PCS_LFPS_RXTERM_IRQ_CLEAR */
|
||
|
|
0x804 /* USB3_UNI_PCS_POWER_DOWN_CONTROL */
|
||
|
|
0x800 /* USB3_UNI_PCS_SW_RESET */
|
||
|
|
0x808>; /* USB3_UNI_PCS_START_CONTROL */
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
|
||
|
|
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
|
||
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
||
|
|
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
|
||
|
|
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
|
||
|
|
|
||
|
|
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
|
||
|
|
"ref_clk", "cfg_ahb_clk";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
|
||
|
|
<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
|
||
|
|
reset-names = "phy_reset", "phy_phy_reset";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|