328 lines
8.5 KiB
C
328 lines
8.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* QTI hardware key manager driver.
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*
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/device.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/crypto.h>
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#include <linux/bitops.h>
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#include <linux/iommu.h>
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#include <linux/hwkm.h>
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#include <linux/tme_hwkm_master.h>
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#include "hwkmregs.h"
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#include "hwkm_serialize.h"
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#include "crypto-qti-ice-regs.h"
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#define ASYNC_CMD_HANDLING false
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// Maximum number of times to poll
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#define MAX_RETRIES 1000
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int retries;
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#define WAIT_UNTIL(cond) \
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for (retries = 0; !(cond) && (retries < MAX_RETRIES); retries++)
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#define ICE_SLAVE_TPKEY_VAL 0x18C
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#define qti_hwkm_readl(hwkm_base, reg, dest) \
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(readl_relaxed(hwkm_base + (reg)))
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#define qti_hwkm_writel(hwkm_base, val, reg, dest) \
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(writel_relaxed((val), hwkm_base + (reg)))
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#define qti_hwkm_setb(hwkm_base, reg, nr, dest) { \
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u32 val = qti_hwkm_readl(hwkm_base, reg, dest); \
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val |= (0x1 << nr); \
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qti_hwkm_writel(hwkm_base, val, reg, dest); \
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}
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#define qti_hwkm_clearb(hwkm_base, reg, nr, dest) { \
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u32 val = qti_hwkm_readl(hwkm_base, reg, dest); \
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val &= ~(0x1 << nr); \
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qti_hwkm_writel(hwkm_base, val, reg, dest); \
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}
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static inline bool qti_hwkm_testb(void __iomem *ice_hwkm_mmio, u32 reg, u8 nr,
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enum hwkm_destination dest)
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{
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u32 val = qti_hwkm_readl(ice_hwkm_mmio, reg, dest);
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val = (val >> nr) & 0x1;
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if (val == 0)
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return false;
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return true;
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}
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static inline unsigned int qti_hwkm_get_reg_data(void __iomem *ice_hwkm_mmio,
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u32 reg, u32 offset, u32 mask,
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enum hwkm_destination dest)
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{
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u32 val = 0;
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val = qti_hwkm_readl(ice_hwkm_mmio, reg, dest);
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return ((val & mask) >> offset);
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}
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static void print_err_info(struct tme_ext_err_info *err)
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{
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pr_err("printing tme hwkm error response\n");
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pr_err("tme_err_status = %d\n", err->tme_err_status);
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pr_err("seq_err_status = %d\n", err->seq_err_status);
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pr_err("seq_kp_err_status0 = %d\n", err->seq_kp_err_status0);
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pr_err("seq_kp_err_status1 = %d\n", err->seq_kp_err_status1);
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}
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static int qti_handle_set_tpkey(const struct hwkm_cmd *cmd_in,
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struct hwkm_rsp *rsp_in)
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{
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int status = 0;
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int retries = 0;
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struct tme_ext_err_info errinfo = {0};
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if (cmd_in->dest != KM_MASTER) {
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pr_err("Invalid dest %d, only master supported\n",
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cmd_in->dest);
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return -EINVAL;
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}
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status = tme_hwkm_master_broadcast_transportkey(&errinfo);
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if (status) {
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if ((status == -ENODEV) || (status == -EAGAIN)) {
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while (((status == -ENODEV) || (status == -EAGAIN)) &&
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(retries < MAX_RETRIES)) {
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usleep_range(8000, 12000);
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status =
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tme_hwkm_master_broadcast_transportkey(
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&errinfo);
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if (status == 0)
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goto ret;
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retries++;
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}
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}
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pr_err("Err in tme hwkm tpkey call, sts = %d\n", status);
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print_err_info(&errinfo);
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}
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ret:
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return status;
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}
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int qti_hwkm_handle_cmd(struct hwkm_cmd *cmd, struct hwkm_rsp *rsp)
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{
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switch (cmd->op) {
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case SET_TPKEY:
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return qti_handle_set_tpkey(cmd, rsp);
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case KEY_UNWRAP_IMPORT:
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case KEY_SLOT_CLEAR:
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case KEY_SLOT_RDWR:
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case SYSTEM_KDF:
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case NIST_KEYGEN:
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case KEY_WRAP_EXPORT:
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case QFPROM_KEY_RDWR: // cmd for HW initialization cmd only
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default:
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return -EINVAL;
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}
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return 0;
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}
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EXPORT_SYMBOL(qti_hwkm_handle_cmd);
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static void qti_hwkm_configure_slot_access(const struct ice_mmio_data *mmio_data)
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{
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qti_hwkm_writel(mmio_data->ice_hwkm_mmio, 0xffffffff,
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QTI_HWKM_ICE_RG_BANK0_AC_BANKN_BBAC_0, ICE_SLAVE);
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qti_hwkm_writel(mmio_data->ice_hwkm_mmio, 0xffffffff,
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QTI_HWKM_ICE_RG_BANK0_AC_BANKN_BBAC_1, ICE_SLAVE);
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qti_hwkm_writel(mmio_data->ice_hwkm_mmio, 0xffffffff,
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QTI_HWKM_ICE_RG_BANK0_AC_BANKN_BBAC_2, ICE_SLAVE);
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qti_hwkm_writel(mmio_data->ice_hwkm_mmio, 0xffffffff,
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QTI_HWKM_ICE_RG_BANK0_AC_BANKN_BBAC_3, ICE_SLAVE);
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qti_hwkm_writel(mmio_data->ice_hwkm_mmio, 0xffffffff,
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QTI_HWKM_ICE_RG_BANK0_AC_BANKN_BBAC_4, ICE_SLAVE);
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}
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static int qti_hwkm_check_bist_status(const struct ice_mmio_data *mmio_data)
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{
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if (!qti_hwkm_testb(mmio_data->ice_hwkm_mmio, QTI_HWKM_ICE_RG_TZ_KM_STATUS,
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BIST_DONE, ICE_SLAVE)) {
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pr_err("%s: Error with BIST_DONE\n", __func__);
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return -EINVAL;
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}
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if (!qti_hwkm_testb(mmio_data->ice_hwkm_mmio, QTI_HWKM_ICE_RG_TZ_KM_STATUS,
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CRYPTO_LIB_BIST_DONE, ICE_SLAVE)) {
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pr_err("%s: Error with CRYPTO_LIB_BIST_DONE\n", __func__);
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return -EINVAL;
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}
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if (!qti_hwkm_testb(mmio_data->ice_hwkm_mmio, QTI_HWKM_ICE_RG_TZ_KM_STATUS,
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BOOT_CMD_LIST1_DONE, ICE_SLAVE)) {
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pr_err("%s: Error with BOOT_CMD_LIST1_DONE\n", __func__);
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return -EINVAL;
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}
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if (!qti_hwkm_testb(mmio_data->ice_hwkm_mmio, QTI_HWKM_ICE_RG_TZ_KM_STATUS,
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BOOT_CMD_LIST0_DONE, ICE_SLAVE)) {
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pr_err("%s: Error with BOOT_CMD_LIST0_DONE\n", __func__);
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return -EINVAL;
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}
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if (!qti_hwkm_testb(mmio_data->ice_hwkm_mmio, QTI_HWKM_ICE_RG_TZ_KM_STATUS,
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KT_CLEAR_DONE, ICE_SLAVE)) {
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pr_err("%s: KT_CLEAR_DONE\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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bool qti_hwkm_init_required(const struct ice_mmio_data *mmio_data)
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{
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u32 val = 0;
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val = ice_readl(mmio_data->ice_base_mmio, ICE_REGS_CONTROL);
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val = val & 0x1;
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return (val == 1);
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}
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EXPORT_SYMBOL(qti_hwkm_init_required);
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static int qti_hwkm_ice_init_sequence(const struct ice_mmio_data *mmio_data)
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{
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int ret = 0;
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u32 val = 0;
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//Put ICE in standard mode
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val = ice_readl(mmio_data->ice_base_mmio, ICE_REGS_CONTROL);
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val = val & 0xFFFFFFFE;
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ice_writel(mmio_data->ice_base_mmio, val, ICE_REGS_CONTROL);
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/* Write memory barrier */
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wmb();
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pr_debug("%s: ICE_REGS_CONTROL = 0x%x\n", __func__,
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ice_readl(mmio_data->ice_base_mmio, ICE_REGS_CONTROL));
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ret = qti_hwkm_check_bist_status(mmio_data);
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if (ret) {
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pr_err("%s: Error in BIST initialization %d\n", __func__, ret);
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return ret;
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}
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// Disable CRC checks
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qti_hwkm_clearb(mmio_data->ice_hwkm_mmio, QTI_HWKM_ICE_RG_TZ_KM_CTL,
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CRC_CHECK_EN, ICE_SLAVE);
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/* Write memory barrier */
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wmb();
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// Configure key slots to be accessed by HLOS
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qti_hwkm_configure_slot_access(mmio_data);
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/* Write memory barrier */
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wmb();
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// Clear RSP_FIFO_FULL bit
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qti_hwkm_setb(mmio_data->ice_hwkm_mmio,
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QTI_HWKM_ICE_RG_BANK0_BANKN_IRQ_STATUS,
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RSP_FIFO_FULL, ICE_SLAVE);
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/* Write memory barrier */
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wmb();
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return ret;
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}
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static void qti_hwkm_enable_slave_receive_mode(
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const struct ice_mmio_data *mmio_data)
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{
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qti_hwkm_clearb(mmio_data->ice_hwkm_mmio,
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QTI_HWKM_ICE_RG_TZ_TPKEY_RECEIVE_CTL, TPKEY_EN, ICE_SLAVE);
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/* Write memory barrier */
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wmb();
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qti_hwkm_writel(mmio_data->ice_hwkm_mmio, ICE_SLAVE_TPKEY_VAL,
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QTI_HWKM_ICE_RG_TZ_TPKEY_RECEIVE_CTL, ICE_SLAVE);
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/* Write memory barrier */
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wmb();
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}
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static void qti_hwkm_disable_slave_receive_mode(
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const struct ice_mmio_data *mmio_data)
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{
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qti_hwkm_clearb(mmio_data->ice_hwkm_mmio,
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QTI_HWKM_ICE_RG_TZ_TPKEY_RECEIVE_CTL, TPKEY_EN, ICE_SLAVE);
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/* Write memory barrier */
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wmb();
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}
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static void qti_hwkm_check_tpkey_status(const struct ice_mmio_data *mmio_data)
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{
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int val = 0;
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val = qti_hwkm_readl(mmio_data->ice_hwkm_mmio,
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QTI_HWKM_ICE_RG_TZ_TPKEY_RECEIVE_STATUS, ICE_SLAVE);
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pr_debug("%s: Tpkey receive status 0x%x\n", __func__, val);
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}
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static int qti_hwkm_set_tpkey(const struct ice_mmio_data *mmio_data)
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{
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int err = 0;
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struct hwkm_cmd cmd_settpkey = {0};
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struct hwkm_rsp rsp_settpkey = {0};
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qti_hwkm_enable_slave_receive_mode(mmio_data);
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cmd_settpkey.op = SET_TPKEY;
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cmd_settpkey.dest = KM_MASTER;
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err = qti_hwkm_handle_cmd(&cmd_settpkey, &rsp_settpkey);
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if (err) {
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pr_err("%s: Error with Set TP key in master %d\n", __func__,
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err);
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return -EINVAL;
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}
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qti_hwkm_check_tpkey_status(mmio_data);
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qti_hwkm_disable_slave_receive_mode(mmio_data);
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return 0;
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}
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int qti_hwkm_init(const struct ice_mmio_data *mmio_data)
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{
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int ret = 0;
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pr_debug("%s %d: HWKM init starts\n", __func__, __LINE__);
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if (!mmio_data->ice_hwkm_mmio || !mmio_data->ice_base_mmio) {
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pr_err("%s: HWKM ICE slave mmio invalid\n", __func__);
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return -EINVAL;
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}
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ret = qti_hwkm_ice_init_sequence(mmio_data);
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if (ret) {
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pr_err("%s: Error in ICE init sequence %d\n", __func__, ret);
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return ret;
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}
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ret = qti_hwkm_set_tpkey(mmio_data);
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if (ret) {
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pr_err("%s: Error setting ICE to receive %d\n", __func__, ret);
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return ret;
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}
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/* Write memory barrier */
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wmb();
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pr_debug("%s %d: HWKM init ends\n", __func__, __LINE__);
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return ret;
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}
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EXPORT_SYMBOL(qti_hwkm_init);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("QTI Hardware Key Manager library");
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