102 lines
3.3 KiB
C
102 lines
3.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDXBAAGHA_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SDXBAAGHA_H
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/* GCC clocks */
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#define GPLL0 0
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#define GPLL0_OUT_EVEN 1
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#define GPLL2 2
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#define GPLL3 3
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#define GPLL4 4
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#define GPLL4_OUT_EVEN 5
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#define GCC_AHB_PCIE_LINK_CLK 6
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#define GCC_EMAC0_AXI_CLK 7
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#define GCC_EMAC0_PHY_AUX_CLK 8
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#define GCC_EMAC0_PHY_AUX_CLK_SRC 9
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#define GCC_EMAC0_PTP_CLK 10
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#define GCC_EMAC0_PTP_CLK_SRC 11
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#define GCC_EMAC0_RGMII_CLK 12
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#define GCC_EMAC0_RGMII_CLK_SRC 13
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#define GCC_EMAC0_SLV_AHB_CLK 14
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#define GCC_EMAC_0_CLKREF_EN 15
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#define GCC_GP1_CLK 16
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#define GCC_GP1_CLK_SRC 17
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#define GCC_GP2_CLK 18
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#define GCC_GP2_CLK_SRC 19
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#define GCC_GP3_CLK 20
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#define GCC_GP3_CLK_SRC 21
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#define GCC_PCIE_0_CLKREF_EN 22
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#define GCC_PCIE_AUX_CLK 23
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#define GCC_PCIE_AUX_CLK_SRC 24
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#define GCC_PCIE_AUX_PHY_CLK_SRC 25
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#define GCC_PCIE_CFG_AHB_CLK 26
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#define GCC_PCIE_MSTR_AXI_CLK 27
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#define GCC_PCIE_PIPE_CLK 28
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#define GCC_PCIE_PIPE_CLK_SRC 29
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#define GCC_PCIE_RCHNG_PHY_CLK 30
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#define GCC_PCIE_RCHNG_PHY_CLK_SRC 31
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#define GCC_PCIE_SLEEP_CLK 32
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#define GCC_PCIE_SLV_AXI_CLK 33
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#define GCC_PCIE_SLV_Q2A_AXI_CLK 34
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#define GCC_PDM2_CLK 35
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#define GCC_PDM2_CLK_SRC 36
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#define GCC_PDM_AHB_CLK 37
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#define GCC_PDM_XO4_CLK 38
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 39
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#define GCC_QUPV3_WRAP0_CORE_CLK 40
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#define GCC_QUPV3_WRAP0_S0_CLK 41
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 42
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#define GCC_QUPV3_WRAP0_S1_CLK 43
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 44
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#define GCC_QUPV3_WRAP0_S2_CLK 45
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 46
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#define GCC_QUPV3_WRAP0_S3_CLK 47
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 48
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#define GCC_QUPV3_WRAP0_S4_CLK 49
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 50
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 51
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 52
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#define GCC_SDCC4_AHB_CLK 53
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#define GCC_SDCC4_APPS_CLK 54
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#define GCC_SDCC4_APPS_CLK_SRC 55
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#define GCC_SNOC_CNOC_USB3_CLK 56
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#define GCC_SYS_NOC_USB_SF_AXI_CLK 57
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#define GCC_USB20_MASTER_CLK 58
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#define GCC_USB20_MASTER_CLK_SRC 59
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#define GCC_USB20_MOCK_UTMI_CLK 60
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#define GCC_USB20_MOCK_UTMI_CLK_SRC 61
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#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 62
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#define GCC_USB20_SLEEP_CLK 63
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#define GCC_USB2_CLKREF_EN 64
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#define GCC_USB3_PRIM_CLKREF_EN 65
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 66
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#define GCC_XO_DIV4_CLK 67
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#define GCC_XO_PCIE_LINK_CLK 68
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#define GCC_BOOT_ROM_AHB_CLK 69
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#define GCC_CPUSS_AHB_CLK 70
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#define GCC_CPUSS_AHB_CLK_SRC 71
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#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 72
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/* GCC resets */
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#define GCC_EMAC0_BCR 0
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#define GCC_PCIE_BCR 1
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#define GCC_PCIE_LINK_DOWN_BCR 2
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#define GCC_PCIE_NOCSR_COM_PHY_BCR 3
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#define GCC_PCIE_PHY_BCR 4
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#define GCC_PCIE_PHY_CFG_AHB_BCR 5
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#define GCC_PCIE_PHY_COM_BCR 6
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#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 7
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#define GCC_PDM_BCR 8
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#define GCC_QUPV3_WRAPPER_0_BCR 9
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#define GCC_QUSB2PHY_BCR 10
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#define GCC_SDCC4_BCR 11
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#define GCC_TCSR_PCIE_BCR 12
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#define GCC_USB20_BCR 13
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 14
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#endif
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