45 lines
1.7 KiB
Text
45 lines
1.7 KiB
Text
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GENI based Qualcomm Technologies Inc Universal Peripheral version 3 (QUPv3)
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I2C controller
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Required properties:
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- compatible: Should be:
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* "qcom,i2c-geni.
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- reg: Should contain QUP register address and length.
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- interrupts: Should contain I2C interrupt.
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- clocks: Serial engine core clock, and AHB clocks needed by the device.
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- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
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should be "active" and "sleep" for the pin confuguration when core is active
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or when entering sleep state.
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- #address-cells: Should be <1> Address cells for i2c device address
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- #size-cells: Should be <0> as i2c addresses have no size component
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- qcom,wrapper-core: Wrapper QUPv3 core containing this I2C controller.
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Optional property:
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- qcom,clk-freq-out : Desired I2C bus clock frequency in Hz.
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When missing default to 400000Hz.
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- qcom,shared : Boolean flag to support multi-ee usecase, used in GSI mode.
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Needs to be added by client driver node in case of multi-ee usecase.
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- qcom,le-vm : Boolean flag to support I2C functionality in trusted VM.
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- qcom,i2c-hub : Boolean flag to support I2C hub functionality.
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Child nodes should conform to i2c bus binding.
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Example:
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i2c@a94000 {
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compatible = "qcom,i2c-geni";
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reg = <0xa94000 0x4000>;
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interrupts = <GIC_SPI 358 0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_i2c_5_active>;
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pinctrl-1 = <&qup_1_i2c_5_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,wrapper-core = <&qupv3_0>;
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qcom,clk-freq-out = <400000>;
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};
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