275 lines
11 KiB
Text
275 lines
11 KiB
Text
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Qualcomm Technologies, Inc. SA410M TLMM block
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This binding describes the Top Level Mode Multiplexer block found in the
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SA410M platform.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be "qcom,sa410m-pinctrl"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: the base address and size of the normal and extended
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TLMM tiles.
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- reg-names:
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Usage: required
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Value type: <prop-encoded-array>
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Defintiion: names for the cells of reg, must contain "normal", "extended".
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify the TLMM summary IRQ.
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- interrupt-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as an interrupt controller
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- #interrupt-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/interrupt-controller/irq.h>
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- gpio-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as a gpio controller
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- #gpio-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/gpio/gpio.h>
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- gpio-ranges:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: see ../gpio/gpio.txt
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- gpio-reserved-ranges:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: see ../gpio/gpio.txt
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
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a general description of GPIO and interrupt bindings.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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PIN CONFIGURATION NODES:
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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- pins:
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Usage: required
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Value type: <string-array>
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Definition: List of gpio pins affected by the properties specified in
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this subnode.
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Valid pins are:
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gpio0-gpio139
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Supports mux, bias and drive-strength
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sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
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sdc2_data sdc1_rclk
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Supports bias and drive-strength
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ufs_reset
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Supports bias and drive-strength
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- function:
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Usage: required
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Value type: <string>
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Definition: Specify the alternative function to be configured for the
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specified pins. Functions are only valid for gpio pins.
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Valid values are:
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msm_mux_gpio, msm_mux_AGERA_PLL_REF, msm_mux_CRI_TRNG_ROSC,
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msm_mux_CRI_TRNG_ROSC0, msm_mux_CRI_TRNG_ROSC1, msm_mux_GCC_GP1_CLK,
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msm_mux_GCC_GP2_CLK, msm_mux_GCC_GP3_CLK, msm_mux_GP0,
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msm_mux_GP1, msm_mux_GP2, msm_mux_JITTER_BIST_REF,
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msm_mux_PA_INDICATOR_OR, msm_mux_PCIE0_CLK_REQ, msm_mux_PLL_BIST_SYNC,
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msm_mux_RGMII0_MDC, msm_mux_RGMII0_MDIO, msm_mux_RGMII0_RXC,
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msm_mux_RGMII0_RXD0, msm_mux_RGMII0_RXD1, msm_mux_RGMII0_RXD2,
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msm_mux_RGMII0_RXD3, msm_mux_RGMII0_RX_CTL, msm_mux_RGMII0_TXC,
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msm_mux_RGMII0_TXD0, msm_mux_RGMII0_TXD1, msm_mux_RGMII0_TXD2,
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msm_mux_RGMII0_TXD3, msm_mux_RGMII0_TX_CTL, msm_mux_SDC1_TB_TRIG,
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msm_mux_SDC2_TB_TRIG, msm_mux_SSBI_WTR1_RX, msm_mux_SSBI_WTR1_TX,
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msm_mux_adsp_ext_vfr, msm_mux_atest_bbrx_dtestout0,
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msm_mux_atest_bbrx_dtestout1, msm_mux_atest_char_start,
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msm_mux_atest_char_status0, msm_mux_atest_char_status1,
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msm_mux_atest_char_status2, msm_mux_atest_char_status3,
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msm_mux_atest_gpsadc0_dtest0, msm_mux_atest_gpsadc0_dtest1,
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msm_mux_atest_gpsadc1_dtest0, msm_mux_atest_gpsadc1_dtest1,
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msm_mux_atest_tsens2_osc, msm_mux_atest_tsens_osc,
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msm_mux_atest_usb1_atereset, msm_mux_atest_usb1_testdataout00,
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msm_mux_atest_usb1_testdataout01, msm_mux_atest_usb1_testdataout02,
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msm_mux_atest_usb1_testdataout03, msm_mux_atest_usb2_atereset,
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msm_mux_atest_usb2_testdataout00, msm_mux_atest_usb2_testdataout01,
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msm_mux_atest_usb2_testdataout02, msm_mux_atest_usb2_testdataout03,
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msm_mux_char_exec_pending, msm_mux_char_exec_release,
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msm_mux_dac_calib_data0, msm_mux_dac_calib_data1,
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msm_mux_dac_calib_data10, msm_mux_dac_calib_data11,
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msm_mux_dac_calib_data12, msm_mux_dac_calib_data13,
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msm_mux_dac_calib_data14, msm_mux_dac_calib_data15,
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msm_mux_dac_calib_data16, msm_mux_dac_calib_data17,
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msm_mux_dac_calib_data18, msm_mux_dac_calib_data19,
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msm_mux_dac_calib_data2, msm_mux_dac_calib_data20,
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msm_mux_dac_calib_data21, msm_mux_dac_calib_data22,
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msm_mux_dac_calib_data23, msm_mux_dac_calib_data24,
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msm_mux_dac_calib_data25, msm_mux_dac_calib_data3,
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msm_mux_dac_calib_data4, msm_mux_dac_calib_data5,
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msm_mux_dac_calib_data6, msm_mux_dac_calib_data7,
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msm_mux_dac_calib_data8, msm_mux_dac_calib_data9,
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msm_mux_dbg_out_clk, msm_mux_ddr_bist_complete,
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msm_mux_ddr_bist_fail, msm_mux_ddr_bist_start,
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msm_mux_ddr_bist_stop, msm_mux_ddr_pxi0_test,
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msm_mux_ddr_pxi1_test, msm_mux_ddr_pxi2_test,
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msm_mux_ddr_pxi3_test, msm_mux_emac0_dll_sdc4,
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msm_mux_emac0_mcg_pst0, msm_mux_emac0_mcg_pst1,
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msm_mux_emac0_mcg_pst2, msm_mux_emac0_mcg_pst3,
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msm_mux_emac0_phy_intr, msm_mux_emac0_ptp_aux,
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msm_mux_emac0_ptp_pps, msm_mux_gsm0_tx_phase,
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msm_mux_gsm1_tx_phase, msm_mux_m_voc_ext,
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msm_mux_mpm_pwr_cllps, msm_mux_mss_lte_coxm,
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msm_mux_nav_gpio0_mira, msm_mux_nav_gpio0_mirb,
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msm_mux_nav_gpio0_mirc, msm_mux_nav_gpio1_mira,
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msm_mux_nav_gpio1_mirb, msm_mux_nav_gpio1_mirc,
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msm_mux_nav_gpio2_mira, msm_mux_nav_gpio2_mirb,
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msm_mux_nav_gpio2_mirc, msm_mux_pbs0, msm_mux_pbs1,
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msm_mux_pbs10, msm_mux_pbs11,
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msm_mux_pbs12, msm_mux_pbs13, msm_mux_pbs14,
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msm_mux_pbs15, msm_mux_pbs2, msm_mux_pbs3,
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msm_mux_pbs4, msm_mux_pbs5, msm_mux_pbs6,
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msm_mux_pbs7, msm_mux_pbs8, msm_mux_pbs9,
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msm_mux_pbs_out_0, msm_mux_pbs_out_1,
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msm_mux_pbs_out_2, msm_mux_phase_flag_status0,
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msm_mux_phase_flag_status1, msm_mux_phase_flag_status10,
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msm_mux_phase_flag_status11, msm_mux_phase_flag_status12,
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msm_mux_phase_flag_status13, msm_mux_phase_flag_status14,
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msm_mux_phase_flag_status15, msm_mux_phase_flag_status16,
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msm_mux_phase_flag_status17, msm_mux_phase_flag_status18,
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msm_mux_phase_flag_status19, msm_mux_phase_flag_status2,
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msm_mux_phase_flag_status20, msm_mux_phase_flag_status21,
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msm_mux_phase_flag_status22, msm_mux_phase_flag_status23,
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msm_mux_phase_flag_status24, msm_mux_phase_flag_status25,
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msm_mux_phase_flag_status26, msm_mux_phase_flag_status27,
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msm_mux_phase_flag_status28, msm_mux_phase_flag_status29,
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msm_mux_phase_flag_status3, msm_mux_phase_flag_status30,
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msm_mux_phase_flag_status31, msm_mux_phase_flag_status4,
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msm_mux_phase_flag_status5, msm_mux_phase_flag_status6,
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msm_mux_phase_flag_status7, msm_mux_phase_flag_status8,
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msm_mux_phase_flag_status9, msm_mux_pll_bypassnl,
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msm_mux_pll_reset_n, msm_mux_prng_rosc_test0,
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msm_mux_prng_rosc_test1, msm_mux_prng_rosc_test2,
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msm_mux_prng_rosc_test3, msm_mux_pwm_0, msm_mux_pwm_1,
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msm_mux_pwm_2, msm_mux_pwm_3, msm_mux_pwm_4,
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msm_mux_pwm_5, msm_mux_pwm_6, msm_mux_pwm_7,
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msm_mux_pwm_8, msm_mux_pwm_9, msm_mux_qdss_cti_trig0,
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msm_mux_qdss_cti_trig1, msm_mux_qdss_gpio_traceclk,
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msm_mux_qdss_gpio_tracectl, msm_mux_qdss_gpio_tracedata0,
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msm_mux_qdss_gpio_tracedata1, msm_mux_qdss_gpio_tracedata10,
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msm_mux_qdss_gpio_tracedata11, msm_mux_qdss_gpio_tracedata12,
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msm_mux_qdss_gpio_tracedata13, msm_mux_qdss_gpio_tracedata14,
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msm_mux_qdss_gpio_tracedata15, msm_mux_qdss_gpio_tracedata2,
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msm_mux_qdss_gpio_tracedata3, msm_mux_qdss_gpio_tracedata4,
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msm_mux_qdss_gpio_tracedata5, msm_mux_qdss_gpio_tracedata6,
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msm_mux_qdss_gpio_tracedata7, msm_mux_qdss_gpio_tracedata8,
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msm_mux_qdss_gpio_tracedata9, msm_mux_qup0_se0_l0,
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msm_mux_qup0_se0_l1, msm_mux_qup0_se0_l2,
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msm_mux_qup0_se0_l3, msm_mux_qup0_se0_l4,
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msm_mux_qup0_se0_l5, msm_mux_qup0_se1_l0,
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msm_mux_qup0_se1_l1, msm_mux_qup0_se1_l2,
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msm_mux_qup0_se1_l3, msm_mux_qup0_se2_l0,
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msm_mux_qup0_se2_l1, msm_mux_qup0_se2_l2,
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msm_mux_qup0_se2_l3, msm_mux_qup0_se3_l0,
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msm_mux_qup0_se3_l1, msm_mux_qup0_se3_l2,
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msm_mux_qup0_se3_l3, msm_mux_qup0_se4_l0,
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msm_mux_qup0_se4_l1, msm_mux_qup0_se4_l2,
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msm_mux_qup0_se4_l3, msm_mux_qup0_se5_l0,
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msm_mux_qup0_se5_l1, msm_mux_qup0_se5_l2,
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msm_mux_qup0_se5_l3, msm_mux_sd_write_protect,
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msm_mux_tgu_ch0_trigout, msm_mux_tgu_ch1_trigout,
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msm_mux_tgu_ch2_trigout, msm_mux_tgu_ch3_trigout,
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msm_mux_tsense_pwm_out, msm_mux_uim1_clk,
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msm_mux_uim1_data, msm_mux_uim1_present,
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msm_mux_uim1_reset, msm_mux_uim2_clk,
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msm_mux_uim2_data, msm_mux_uim2_present,
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msm_mux_uim2_reset, msm_mux_usb0_phy_ps,
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msm_mux_vfr_1, msm_mux_vsense_trigger_mirnat,
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msm_mux_wlan1_adc_dtest0, msm_mux_wlan1_adc_dtest1,
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msm_mux_NA
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- bias-disable:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as no pull.
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- bias-pull-down:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as pull down.
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- bias-pull-up:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as pull up.
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- output-high:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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high.
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Not valid for sdc pins.
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- output-low:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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low.
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Not valid for sdc pins.
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- drive-strength:
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Usage: optional
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Value type: <u32>
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Definition: Selects the drive strength for the specified pins, in mA.
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Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
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Example:
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tlmm: pinctrl@500000 {
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compatible = "qcom,sa410-pinctrl";
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reg = <0x500000 0x300000>;
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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wakeup-parent = <&pdc>;
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};
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