150 lines
3.3 KiB
Text
150 lines
3.3 KiB
Text
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/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&tlmm {
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sar_int_default: sar_int_default {
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mux {
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pins = "gpio127";
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function = "gpio";
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};
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config {
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pins = "gpio127";
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num-grp-pins = <1>;
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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sar_int_sleep: sar_int_sleep {
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mux {
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pins = "gpio127";
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function = "gpio";
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};
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config {
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pins = "gpio127";
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num-grp-pins = <1>;
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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&qupv3_se8_i2c {
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status = "ok";
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sx937x@2c { /* SAR sensor */
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compatible = "Semtech,sx937x";
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reg = <0x2c>;
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Semtech,power-supply-type = <0>;
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cap_vdd-supply = <&pm7550_l7>;
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pinctrl-names = "default","sleep";
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pinctrl-0 = <&sar_int_default>;
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pinctrl-1 = <&sar_int_sleep>;
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interrupt-parent = <&tlmm>;
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interrupts = <127 0x02>;
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interrupt-names = "capsense0_irq";
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Semtech,nirq-gpio= <&tlmm 127 0x02>;
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/*use PH4/5/6 as the reference sensor
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set it to 0xff if the ref-phases-x is not used*/
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Semtech,ref-phases-a = <4>;
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Semtech,ref-phases-b = <5>;
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Semtech,ref-phases-c = <6>;
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Semtech,button-flag = <0x1f>;
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Semtech,reg-num = <63>;
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Semtech,reg-init = <
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0x4004 0x74
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0x8020 0x32
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0x8028 0x46E
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0x8034 0x46E
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0x8040 0x46E
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0x804C 0x46E
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0x8058 0x46E
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0x8064 0x46E
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0x8070 0x46E
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0x807C 0x85C
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0x8030 0x924925
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0x803C 0x92C924
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0x8048 0x964924
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0x8054 0xB24924
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0x8060 0x92492C
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0x806C 0x924964
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0x8078 0x925924
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0x8084 0x0
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0x8098 0x7739
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0x80B8 0x7840
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0x80D8 0x824D
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0x80F8 0x2B2B
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0x8118 0x6540
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0x8138 0x0
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0x8158 0x0
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0x8178 0x0
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0x80A0 0x22220001
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0x80C0 0x14140002
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0x80E0 0x20200002
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0x8100 0x1B210003
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0x8120 0x1D1D0003
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0x8140 0x0
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0x8160 0x0
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0x8180 0x0
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0x8188 0x8000014
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0x818C 0x8000015
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0x8190 0x8000016
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0x8194 0x0
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0x8090 0x2AD67000
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0x80B0 0x2DD67000
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0x80D0 0x2DD67000
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0x80F0 0x1CD67000
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0x8110 0x2DD67000
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0x8130 0x2AD67000
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0x8150 0x0
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0x8170 0x0
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0x8088 0x300000
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0x80A8 0x300000
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0x80C8 0x300000
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0x80E8 0x300000
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0x8108 0x300000
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0x8128 0x300000
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0x8148 0x300000
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0x8168 0x0
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0x808C 0xE0600080
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0x80AC 0xE0600080
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0x80CC 0xE0600080
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0x80EC 0xE0600080
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0x810C 0xE06000C0
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0x812C 0xE06000C0
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0x814C 0xE0600018
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0x816C 0x0
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0x8024 0x7F00
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>;
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status = "ok";
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};
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awinic_sar@12 {
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/* common node */
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compatible = "awinic,aw_sar";
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reg = < 0x12 >;
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//aw_sar,regulator-power-supply = <1>;
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sar-num = < 0 >;
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interrupt-parent = < &tlmm >;
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interrupts = <127 0x02>;
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interrupt-names = "awinic_irq";
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irq-gpio = <&tlmm 127 0x02>;
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//vcc0-supply = <&L12A>;
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channel_use_flag = <0x1f>;
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aw_sar,use_plug_cail;
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aw_sar,update_fw;
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/* private node belongs to aw963xx */
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start-mode = < 1 >; // 0: start in rom 1: start in ram
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irq-mux = < 2 >; // set csx as irq pin. config this field when connect to aw96308/aw96310
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status = "okay";
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};
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};
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