603 lines
14 KiB
Text
603 lines
14 KiB
Text
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#include <dt-bindings/clock/qcom,gcc-lemans.h>
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#include <dt-bindings/gpio/gpio.h>
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&soc {
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pcie0: qcom,pcie@0x01c00000 {
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compatible = "qcom,pci-msm";
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reg = <0x01c00000 0x3000>,
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<0x1c04000 0x2000>,
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<0x40000000 0xf20>,
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<0x40000f20 0xa8>,
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<0x40001000 0x4000>,
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<0x40100000 0x100000>,
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<0x01c03000 0x1000>;
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reg-names = "parf", "phy", "dm_core", "elbi",
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"iatu", "conf", "mhi";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
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perst-gpio = <&tlmm 2 GPIO_ACTIVE_HIGH>;
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wake-gpio = <&tlmm 0 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_perst_default
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&pcie0_clkreq_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_perst_default
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&pcie0_clkreq_sleep
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&pcie0_wake_default>;
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gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
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vreg-1p2-supply = <&L1C>;
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vreg-0p9-supply = <&L5A>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-mx-supply = <&VDD_MXC_LEVEL>;
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qcom,vreg-1p2-voltage-level = <1200000 1200000 25800>;
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qcom,vreg-0p9-voltage-level = <880000 880000 186000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_SVS_L1
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RPMH_REGULATOR_LEVEL_SVS_L1
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_SVS_L1
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RPMH_REGULATOR_LEVEL_SVS_L1
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_SVS_L1
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RPMH_REGULATOR_LEVEL_SVS_L1
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100000000
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/* Gen4 */
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RPMH_REGULATOR_LEVEL_NOM
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RPMH_REGULATOR_LEVEL_NOM
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100000000>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&rpmh_cxo_clk>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_CLKREF_EN>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
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<&gcc GCC_PCIE_0_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
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<&pcie_0_pipe_clk>;
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clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo",
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"pcie_0_slv_q2a_axi_clk", "pcie_phy_refgen_clk",
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"pcie_pipe_clk_mux", "pcie_phy_aux_clk",
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"pcie_0_pipediv2_clk",
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"pcie_pipe_clk_ext_src";
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clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <100000000>, <0>,
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<0>, <0>, <0>;
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clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
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<0>, <0>, <0>, <0>, <0>, <0>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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dma-coherent;
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msi-parent = <&pcie0_msi_snps>;
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qcom,smmu-sid-base = <0x0000>;
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iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
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<0x100 &pcie_smmu 0x0001 0x1>,
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<0x200 &pcie_smmu 0x0002 0x1>,
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<0x300 &pcie_smmu 0x0003 0x1>,
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<0x400 &pcie_smmu 0x0004 0x1>,
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<0x500 &pcie_smmu 0x0005 0x1>,
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<0x600 &pcie_smmu 0x0006 0x1>,
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<0x700 &pcie_smmu 0x0007 0x1>,
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<0x800 &pcie_smmu 0x0008 0x1>,
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<0x900 &pcie_smmu 0x0009 0x1>,
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<0xa00 &pcie_smmu 0x000a 0x1>,
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<0xb00 &pcie_smmu 0x000b 0x1>,
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<0xc00 &pcie_smmu 0x000c 0x1>,
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<0xd00 &pcie_smmu 0x000d 0x1>,
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<0xe00 &pcie_smmu 0x000e 0x1>,
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<0xf00 &pcie_smmu 0x000f 0x1>;
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qcom,boot-option = <0x1>;
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qcom,aux-clk-freq = <20>; /* 19.2 MHz */
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qcom,slv-addr-space-size = <0x1fd00000>;
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qcom,ep-latency = <10>;
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qcom,core-preset = <0x77777777>;
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qcom,pcie-phy-ver = <109>;
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qcom,phy-status-offset = <0x1214>;
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qcom,phy-status-bit = <7>;
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qcom,phy-power-down-offset = <0x1240>;
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qcom,phy-sequence = <0x1240 0x03 0x0
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0x1010 0x00 0x0
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0x101c 0x31 0x0
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0x1020 0x01 0x0
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0x1024 0xde 0x0
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0x1028 0x07 0x0
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0x1030 0x97 0x0
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0x1034 0x0c 0x0
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0x1044 0x14 0x0
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0x1048 0x90 0x0
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0x1058 0x0f 0x0
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0x1074 0x06 0x0
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0x1078 0x06 0x0
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0x107c 0x16 0x0
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0x1080 0x16 0x0
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0x1084 0x36 0x0
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0x1088 0x36 0x0
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0x1094 0x08 0x0
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0x10a4 0x46 0x0
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0x10a8 0x04 0x0
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0x10ac 0x0a 0x0
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0x10b0 0x1a 0x0
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0x10b4 0x14 0x0
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0x10b8 0x34 0x0
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0x10bc 0x82 0x0
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0x10c4 0xd0 0x0
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0x10cc 0x55 0x0
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0x10d0 0x55 0x0
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0x10d4 0x03 0x0
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0x10d8 0x55 0x0
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0x10dc 0x55 0x0
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0x10e0 0x05 0x0
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0x110c 0x02 0x0
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0x1154 0x34 0x0
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0x1158 0x12 0x0
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0x115c 0x00 0x0
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0x1168 0x0a 0x0
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0x116c 0x04 0x0
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0x119c 0x88 0x0
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0x1174 0x60 0x0
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0x117c 0x06 0x0
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0x11a0 0x14 0x0
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0x11a8 0x0f 0x0
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0x0220 0x16 0x0
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0x03c0 0x38 0x0
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0x0a20 0x16 0x0
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0x0bc0 0x38 0x0
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0x0360 0x9a 0x0
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0x0364 0xb0 0x0
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0x0368 0x92 0x0
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0x036c 0xf0 0x0
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0x0370 0x42 0x0
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0x0374 0x99 0x0
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0x0378 0x29 0x0
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0x037c 0x9a 0x0
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0x0380 0xfb 0x0
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0x0384 0x92 0x0
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0x0388 0xec 0x0
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0x038c 0x43 0x0
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0x0390 0xdd 0x0
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0x0394 0x0d 0x0
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0x0398 0xf3 0x0
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0x039c 0xf8 0x0
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0x03a0 0xec 0x0
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0x03a4 0xd6 0x0
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0x03a8 0x83 0x0
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0x03ac 0xf5 0x0
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0x03b0 0x5e 0x0
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0x0b60 0x9a 0x0
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0x0b64 0xb0 0x0
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0x0b68 0x92 0x0
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0x0b6c 0xf0 0x0
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0x0b70 0x42 0x0
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0x0b74 0x99 0x0
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0x0b78 0x29 0x0
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0x0b7c 0x9a 0x0
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0x0b80 0xfb 0x0
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0x0b84 0x92 0x0
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0x0b88 0xec 0x0
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0x0b8c 0x43 0x0
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0x0b90 0xdd 0x0
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0x0b94 0x0d 0x0
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0x0b98 0xf3 0x0
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0x0b9c 0xf8 0x0
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0x0ba0 0xec 0x0
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0x0ba4 0xd6 0x0
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0x0ba8 0x83 0x0
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0x0bac 0xf5 0x0
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0x0bb0 0x5e 0x0
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0x03b4 0x20 0x0
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0x022c 0x3f 0x0
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0x0230 0x37 0x0
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0x0bb4 0x20 0x0
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0x0a2c 0x3f 0x0
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0x0a30 0x37 0x0
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0x0078 0x05 0x0
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0x007c 0xf6 0x0
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0x0080 0x0f 0x0
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0x0878 0x05 0x0
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0x087c 0xf6 0x0
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0x0880 0x0f 0x0
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0x0290 0x00 0x0
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0x0a90 0x00 0x0
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0x03f8 0x1f 0x0
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0x0400 0x1f 0x0
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0x0408 0x1f 0x0
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0x0410 0x1f 0x0
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0x0418 0x1f 0x0
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0x0420 0x1f 0x0
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0x03f4 0x1f 0x0
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0x03fc 0x1f 0x0
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0x0404 0x1f 0x0
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0x0bf8 0x1f 0x0
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0x0c00 0x1f 0x0
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0x0c08 0x1f 0x0
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0x0c10 0x1f 0x0
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0x0c18 0x1f 0x0
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0x0c20 0x1f 0x0
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0x0bf4 0x1f 0x0
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0x0bfc 0x1f 0x0
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0x0c04 0x1f 0x0
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0x0438 0x09 0x0
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0x0c38 0x09 0x0
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0x0208 0x0c 0x0
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0x0a08 0x0c 0x0
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0x020c 0x08 0x0
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0x0a0c 0x08 0x0
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0x021c 0x04 0x0
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0x0a1c 0x04 0x0
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0x02d4 0x04 0x0
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0x0ad4 0x04 0x0
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0x02dc 0x08 0x0
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0x0adc 0x08 0x0
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0x0308 0x0b 0x0
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0x0b08 0x0b 0x0
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0x0318 0x7c 0x0
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0x0b18 0x7c 0x0
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0x027c 0x10 0x0
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0x0a7c 0x10 0x0
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0x02b4 0x00 0x0
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0x0ab4 0x00 0x0
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0x02ec 0x05 0x0
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0x0aec 0x05 0x0
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0x02c4 0x00 0x0
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0x02c8 0x1f 0x0
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0x0ac4 0x00 0x0
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0x0ac8 0x1f 0x0
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0x0030 0x1f 0x0
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0x0034 0x07 0x0
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0x0830 0x1f 0x0
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0x0834 0x07 0x0
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0x141c 0xc1 0x0
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0x1490 0x00 0x0
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0x13e0 0x16 0x0
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0x13e4 0x22 0x0
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0x1508 0x02 0x0
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0x14a0 0x16 0x0
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0x1584 0x28 0x0
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0x1370 0x2e 0x0
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0x155c 0x2e 0x0
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0x140c 0x1d 0x0
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0x1388 0x66 0x0
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0x1e24 0x00 0x0
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0x1e28 0x00 0x0
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0x1828 0x00 0x0
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0x1c28 0x00 0x0
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0x127c 0x00 0x0
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0x1260 0x00 0x0
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0x1200 0x00 0x0
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0x1244 0x03 0x0>;
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status = "disabled";
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pcie0_rp: pcie0_rp {
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|
|
reg = <0 0 0 0 0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie1: qcom,pcie@0x01c10000 {
|
||
|
|
compatible = "qcom,pci-msm";
|
||
|
|
|
||
|
|
reg = <0x01c10000 0x3000>,
|
||
|
|
<0x01c14000 0x4000>,
|
||
|
|
<0x60000000 0xf20>,
|
||
|
|
<0x60000f20 0xa8>,
|
||
|
|
<0x60001000 0x4000>,
|
||
|
|
<0x60100000 0x100000>,
|
||
|
|
<0x01c13000 0x1000>;
|
||
|
|
reg-names = "parf", "phy", "dm_core",
|
||
|
|
"elbi", "iatu", "conf", "mhi";
|
||
|
|
|
||
|
|
cell-index = <1>;
|
||
|
|
linux,pci-domain = <1>;
|
||
|
|
|
||
|
|
#address-cells = <3>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
|
||
|
|
<0x02000000 0x0 0x60300000 0x60300000 0x0 0x1fd00000>;
|
||
|
|
|
||
|
|
interrupt-parent = <&pcie1>;
|
||
|
|
interrupts = <0 1 2 3 4>;
|
||
|
|
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
|
||
|
|
"int_d";
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
interrupt-map-mask = <0 0 0 0xffffffff>;
|
||
|
|
interrupt-map = <0 0 0 0 &intc 0 GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH
|
||
|
|
0 0 0 1 &intc 0 GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH
|
||
|
|
0 0 0 2 &intc 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
|
||
|
|
0 0 0 3 &intc 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
|
||
|
|
0 0 0 4 &intc 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
|
||
|
|
perst-gpio = <&tlmm 4 GPIO_ACTIVE_HIGH>;
|
||
|
|
wake-gpio = <&tlmm 5 GPIO_ACTIVE_HIGH>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&pcie1_perst_default
|
||
|
|
&pcie1_clkreq_default
|
||
|
|
&pcie1_wake_default>;
|
||
|
|
pinctrl-1 = <&pcie1_perst_default
|
||
|
|
&pcie1_clkreq_sleep
|
||
|
|
&pcie1_wake_default>;
|
||
|
|
|
||
|
|
gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>;
|
||
|
|
vreg-1p2-supply = <&L1C>;
|
||
|
|
vreg-0p9-supply = <&L5A>;
|
||
|
|
vreg-cx-supply = <&VDD_CX_LEVEL>;
|
||
|
|
vreg-mx-supply = <&VDD_MXC_LEVEL>;
|
||
|
|
|
||
|
|
qcom,vreg-1p2-voltage-level = <1200000 1200000 33300>;
|
||
|
|
qcom,vreg-0p9-voltage-level = <880000 880000 439000>;
|
||
|
|
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
||
|
|
RPMH_REGULATOR_LEVEL_NOM 0>;
|
||
|
|
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
||
|
|
RPMH_REGULATOR_LEVEL_NOM 0>;
|
||
|
|
|
||
|
|
qcom,bw-scale = /* Gen1 */
|
||
|
|
<RPMH_REGULATOR_LEVEL_SVS_L1
|
||
|
|
RPMH_REGULATOR_LEVEL_SVS_L1
|
||
|
|
19200000
|
||
|
|
/* Gen2 */
|
||
|
|
RPMH_REGULATOR_LEVEL_SVS_L1
|
||
|
|
RPMH_REGULATOR_LEVEL_SVS_L1
|
||
|
|
19200000
|
||
|
|
/* Gen3 */
|
||
|
|
RPMH_REGULATOR_LEVEL_SVS_L1
|
||
|
|
RPMH_REGULATOR_LEVEL_SVS_L1
|
||
|
|
100000000
|
||
|
|
/* Gen4 */
|
||
|
|
RPMH_REGULATOR_LEVEL_NOM
|
||
|
|
RPMH_REGULATOR_LEVEL_NOM
|
||
|
|
100000000>;
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
|
||
|
|
<&rpmh_cxo_clk>,
|
||
|
|
<&gcc GCC_PCIE_1_AUX_CLK>,
|
||
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
||
|
|
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
||
|
|
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
|
||
|
|
<&gcc GCC_PCIE_CLKREF_EN>,
|
||
|
|
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
|
||
|
|
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
|
||
|
|
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
|
||
|
|
<&gcc GCC_PCIE_1_PHY_AUX_CLK>,
|
||
|
|
<&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
|
||
|
|
<&pcie_1_pipe_clk>;
|
||
|
|
|
||
|
|
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
|
||
|
|
"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
|
||
|
|
"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
|
||
|
|
"pcie_1_ldo",
|
||
|
|
"pcie_1_slv_q2a_axi_clk", "pcie_phy_refgen_clk",
|
||
|
|
"pcie_pipe_clk_mux", "pcie_phy_aux_clk",
|
||
|
|
"pcie_1_pipediv2_clk",
|
||
|
|
"pcie_pipe_clk_ext_src";
|
||
|
|
|
||
|
|
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
|
||
|
|
<0>, <0>, <100000000>, <0>,
|
||
|
|
<0>, <0>, <0>;
|
||
|
|
|
||
|
|
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
|
||
|
|
<0>, <0>, <0>, <0>, <0>, <0>;
|
||
|
|
|
||
|
|
resets = <&gcc GCC_PCIE_1_BCR>,
|
||
|
|
<&gcc GCC_PCIE_1_PHY_BCR>;
|
||
|
|
reset-names = "pcie_1_core_reset",
|
||
|
|
"pcie_1_phy_reset";
|
||
|
|
|
||
|
|
dma-coherent;
|
||
|
|
|
||
|
|
msi-parent = <&pcie1_msi_snps>;
|
||
|
|
qcom,smmu-sid-base = <0x0080>;
|
||
|
|
iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
|
||
|
|
<0x100 &pcie_smmu 0x0081 0x1>,
|
||
|
|
<0x200 &pcie_smmu 0x0082 0x1>,
|
||
|
|
<0x300 &pcie_smmu 0x0083 0x1>,
|
||
|
|
<0x400 &pcie_smmu 0x0084 0x1>,
|
||
|
|
<0x500 &pcie_smmu 0x0085 0x1>,
|
||
|
|
<0x600 &pcie_smmu 0x0086 0x1>,
|
||
|
|
<0x700 &pcie_smmu 0x0087 0x1>,
|
||
|
|
<0x800 &pcie_smmu 0x0088 0x1>,
|
||
|
|
<0x900 &pcie_smmu 0x0089 0x1>,
|
||
|
|
<0xa00 &pcie_smmu 0x008a 0x1>,
|
||
|
|
<0xb00 &pcie_smmu 0x008b 0x1>,
|
||
|
|
<0xc00 &pcie_smmu 0x008c 0x1>,
|
||
|
|
<0xd00 &pcie_smmu 0x008d 0x1>,
|
||
|
|
<0xe00 &pcie_smmu 0x008e 0x1>,
|
||
|
|
<0xf00 &pcie_smmu 0x008f 0x1>;
|
||
|
|
|
||
|
|
qcom,boot-option = <0x0>;
|
||
|
|
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
|
||
|
|
qcom,slv-addr-space-size = <0x1fd00000>;
|
||
|
|
qcom,ep-latency = <10>;
|
||
|
|
qcom,core-preset = <0x77777777>;
|
||
|
|
|
||
|
|
qcom,pcie-phy-ver = <1093>;
|
||
|
|
qcom,phy-status-offset = <0x2214>;
|
||
|
|
qcom,phy-status-bit = <7>;
|
||
|
|
qcom,phy-power-down-offset = <0x2240>;
|
||
|
|
|
||
|
|
qcom,phy-sequence = <0x2240 0x03 0x0
|
||
|
|
0x2010 0x00 0x0
|
||
|
|
0x201c 0x31 0x0
|
||
|
|
0x2020 0x01 0x0
|
||
|
|
0x2024 0xde 0x0
|
||
|
|
0x2028 0x07 0x0
|
||
|
|
0x2030 0x97 0x0
|
||
|
|
0x2034 0x0c 0x0
|
||
|
|
0x2044 0x1c 0x0
|
||
|
|
0x2048 0x90 0x0
|
||
|
|
0x2058 0x0f 0x0
|
||
|
|
0x2074 0x06 0x0
|
||
|
|
0x2078 0x06 0x0
|
||
|
|
0x207c 0x16 0x0
|
||
|
|
0x2080 0x16 0x0
|
||
|
|
0x2084 0x36 0x0
|
||
|
|
0x2088 0x36 0x0
|
||
|
|
0x2094 0x08 0x0
|
||
|
|
0x20a4 0x46 0x0
|
||
|
|
0x20a8 0x04 0x0
|
||
|
|
0x20ac 0x0a 0x0
|
||
|
|
0x20b0 0x1a 0x0
|
||
|
|
0x20b4 0x14 0x0
|
||
|
|
0x20b8 0x34 0x0
|
||
|
|
0x20bc 0x82 0x0
|
||
|
|
0x20c4 0xd0 0x0
|
||
|
|
0x20cc 0x55 0x0
|
||
|
|
0x20d0 0x55 0x0
|
||
|
|
0x20d4 0x03 0x0
|
||
|
|
0x20d8 0x55 0x0
|
||
|
|
0x20dc 0x55 0x0
|
||
|
|
0x20e0 0x05 0x0
|
||
|
|
0x210c 0x02 0x0
|
||
|
|
0x2154 0x34 0x0
|
||
|
|
0x2158 0x12 0x0
|
||
|
|
0x215c 0x00 0x0
|
||
|
|
0x2168 0x0a 0x0
|
||
|
|
0x216c 0x04 0x0
|
||
|
|
0x219c 0x88 0x0
|
||
|
|
0x2174 0x60 0x0
|
||
|
|
0x217c 0x06 0x0
|
||
|
|
0x21a0 0x14 0x0
|
||
|
|
0x21a8 0x0f 0x0
|
||
|
|
0x3a2c 0x3f 0x0
|
||
|
|
0x3a30 0x37 0x0
|
||
|
|
0x3a90 0x00 0x0
|
||
|
|
0x3bc0 0x38 0x0
|
||
|
|
0x3ab4 0x00 0x0
|
||
|
|
0x3aec 0x05 0x0
|
||
|
|
0x3bb4 0x20 0x0
|
||
|
|
0x3b08 0x0b 0x0
|
||
|
|
0x3b18 0x7c 0x0
|
||
|
|
0x3a7c 0x10 0x0
|
||
|
|
0x3bf4 0x1f 0x0
|
||
|
|
0x3bf8 0x1f 0x0
|
||
|
|
0x3bfc 0x1f 0x0
|
||
|
|
0x3c00 0x1f 0x0
|
||
|
|
0x3c04 0x1f 0x0
|
||
|
|
0x3c08 0x1f 0x0
|
||
|
|
0x3c10 0x1f 0x0
|
||
|
|
0x3c18 0x1f 0x0
|
||
|
|
0x3c20 0x1f 0x0
|
||
|
|
0x3c38 0x09 0x0
|
||
|
|
0x3b60 0x9a 0x0
|
||
|
|
0x3b64 0xb0 0x0
|
||
|
|
0x3b68 0x92 0x0
|
||
|
|
0x3b6c 0xf0 0x0
|
||
|
|
0x3b70 0x42 0x0
|
||
|
|
0x3b74 0x99 0x0
|
||
|
|
0x3b78 0x29 0x0
|
||
|
|
0x3b7c 0x9a 0x0
|
||
|
|
0x3b80 0xb6 0x0
|
||
|
|
0x3b84 0x92 0x0
|
||
|
|
0x3b88 0xf0 0x0
|
||
|
|
0x3b8c 0x43 0x0
|
||
|
|
0x3b90 0xdd 0x0
|
||
|
|
0x3b94 0x0d 0x0
|
||
|
|
0x3b98 0xf3 0x0
|
||
|
|
0x3b9c 0xf6 0x0
|
||
|
|
0x3ba0 0xee 0x0
|
||
|
|
0x3ba4 0xd2 0x0
|
||
|
|
0x3ba8 0x83 0x0
|
||
|
|
0x3bac 0xf9 0x0
|
||
|
|
0x3bb0 0x3d 0x0
|
||
|
|
0x3ac4 0x00 0x0
|
||
|
|
0x3ac8 0x1f 0x0
|
||
|
|
0x3a08 0x0c 0x0
|
||
|
|
0x3a0c 0x08 0x0
|
||
|
|
0x3a1c 0x04 0x0
|
||
|
|
0x3a20 0x16 0x0
|
||
|
|
0x3ad4 0x04 0x0
|
||
|
|
0x3adc 0x08 0x0
|
||
|
|
0x3878 0x05 0x0
|
||
|
|
0x387c 0xf6 0x0
|
||
|
|
0x3880 0x0f 0x0
|
||
|
|
0x3834 0x07 0x0
|
||
|
|
0x3830 0x1f 0x0
|
||
|
|
0x241c 0xc1 0x0
|
||
|
|
0x2490 0x00 0x0
|
||
|
|
0x23e0 0x16 0x0
|
||
|
|
0x23e4 0x22 0x0
|
||
|
|
0x2508 0x02 0x0
|
||
|
|
0x24a0 0x16 0x0
|
||
|
|
0x2584 0x28 0x0
|
||
|
|
0x2370 0x2e 0x0
|
||
|
|
0x255c 0x2e 0x0
|
||
|
|
0x2388 0x66 0x0
|
||
|
|
0x240c 0x1d 0x0
|
||
|
|
0x2200 0x00 0x0
|
||
|
|
0x2244 0x03 0x0>;
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pcie1_rp: pcie1_rp {
|
||
|
|
reg = <0 0 0 0 0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie0_msi_snps: qcom,pcie0_msi@a0000000 {
|
||
|
|
compatible = "qcom,pci-msi";
|
||
|
|
msi-controller;
|
||
|
|
reg = <0xa0000000 0x0>;
|
||
|
|
interrupt-parent = <&intc>;
|
||
|
|
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
qcom,snps;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie1_msi_snps: qcom,pcie1_msi@a0000000 {
|
||
|
|
compatible = "qcom,pci-msi";
|
||
|
|
msi-controller;
|
||
|
|
reg = <0xa0000000 0x0>;
|
||
|
|
interrupt-parent = <&intc>;
|
||
|
|
interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
qcom,snps;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|