513 lines
16 KiB
Text
513 lines
16 KiB
Text
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/ {
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aliases {
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spi1 = &spi_1;
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spi2 = &spi_2;
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spi3 = &spi_3;
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spi4 = &spi_4;
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spi5 = &spi_5;
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spi6 = &spi_6;
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i2c1 = &i2c_1;
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i2c2 = &i2c_2;
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i2c3 = &i2c_3;
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i2c4 = &i2c_4;
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i2c5 = &i2c_5;
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i2c6 = &i2c_6;
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};
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};
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&soc {
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/* Debug UART Instance */
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blsp1_uart2_console: serial@78b1000 {
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compatible = "qcom,msm-uartdm", "qcom,msm-uartdm-v1.4";
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reg = <0x78b1000 0x200>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "active", "sleep";
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pinctrl-0 = <&blsp_uart_tx_a2_active
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&blsp_uart_rx_a2_active>;
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pinctrl-1 = <&blsp_uart_tx_rx_a2_sleep>;
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status = "disabled";
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};
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dma_blsp1: qcom,sps-dma@7884000{ /* BLSP1 */
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#dma-cells = <4>;
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compatible = "qcom,sps-dma";
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reg = <0x7884000 0x25000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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qcom,summing-threshold = <0x10>;
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};
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dma_blsp2: qcom,sps-dma@7ac4000{ /* BLSP2 */
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#dma-cells = <4>;
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compatible = "qcom,sps-dma";
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reg = <0x7ac4000 0x17000>;
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interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
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qcom,summing-threshold = <0x10>;
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};
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i2c_1: i2c@78b5000 { /* BLSP1 QUP0 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78b5000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
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<&dma_blsp1 9 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_1_active>;
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pinctrl-1 = <&i2c_1_sleep>;
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status = "disabled";
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};
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i2c_2: i2c@78b6000 { /* BLSP1 QUP1 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78b6000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
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<&dma_blsp1 11 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_2_active>;
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pinctrl-1 = <&i2c_2_sleep>;
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status = "disabled";
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};
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i2c_3: i2c@78b7000 { /* BLSP1 QUP2 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78b7000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 12 64 0x20000020 0x20>,
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<&dma_blsp1 13 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_3_sda_active>, <&i2c_3_scl_active>;
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pinctrl-1 = <&i2c_3_sleep>;
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status = "disabled";
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};
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i2c_4: i2c@78b8000 { /* BLSP1 QUP3 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78b8000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 14 64 0x20000020 0x20>,
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<&dma_blsp1 15 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_4_active>;
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pinctrl-1 = <&i2c_4_sleep>;
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status = "disabled";
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};
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i2c_5: i2c@78b9000 { /* BLSP1 QUP4 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78b9000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 16 64 0x20000020 0x20>,
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<&dma_blsp1 17 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_5_active>;
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pinctrl-1 = <&i2c_5_sleep>;
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status = "disabled";
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};
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i2c_6: i2c@7af5000 { /* BLSP2 QUP0 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x7af5000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp2 2 64 0x20000020 0x20>,
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<&dma_blsp2 3 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_2 &bimc SLAVE_EBI_CH0>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP2_AHB_CLK>,
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<&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_6_active>;
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pinctrl-1 = <&i2c_6_sleep>;
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status = "disabled";
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};
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spi_1: spi@78b5000 { /* BLSP1 QUP0 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x78b5000 0x600>,
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<0x7884000 0x25000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <8>;
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qcom,bam-producer-pipe-index = <9>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_1_active>;
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pinctrl-1 = <&spi_1_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_2: spi@78b6000 { /* BLSP1 QUP1 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x78b6000 0x600>,
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<0x7884000 0x25000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <25000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <10>;
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qcom,bam-producer-pipe-index = <11>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_2_mosi_a1_active
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&spi_2_miso_a1_active
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&spi_2_cs_n_a1_active
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&spi_2_clk_a1_active>;
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pinctrl-1 = <&spi_2_mosi_a1_sleep
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&spi_2_miso_a1_sleep
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&spi_2_cs_n_a1_sleep
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&spi_2_clk_a1_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_3: spi@78b7000 { /* BLSP1 QUP2 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x78b7000 0x600>,
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<0x7884000 0x25000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <25000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <12>;
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qcom,bam-producer-pipe-index = <13>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_3_active>;
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pinctrl-1 = <&spi_3_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_4: spi@78b8000 { /* BLSP1 QUP3 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x78b8000 0x600>,
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<0x7884000 0x25000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <14>;
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qcom,bam-producer-pipe-index = <15>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_4_active>;
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pinctrl-1 = <&spi_4_sleep>;
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clock-names = "iface_clk", "core_clk";
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|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||
|
|
<&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spi_5: spi@78b9000 { /* BLSP1 QUP4 */
|
||
|
|
compatible = "qcom,spi-qup-v2";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg-names = "spi_physical", "spi_bam_physical";
|
||
|
|
reg = <0x78b9000 0x600>,
|
||
|
|
<0x7884000 0x25000>;
|
||
|
|
interrupt-names = "spi_irq", "spi_bam_irq";
|
||
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,use-bam;
|
||
|
|
qcom,ver-reg-exists;
|
||
|
|
qcom,bam-consumer-pipe-index = <16>;
|
||
|
|
qcom,bam-producer-pipe-index = <17>;
|
||
|
|
interconnect-names = "blsp-ddr";
|
||
|
|
interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
qcom,use-pinctrl;
|
||
|
|
pinctrl-names = "spi_default", "spi_sleep";
|
||
|
|
pinctrl-0 = <&spi_5_active>;
|
||
|
|
pinctrl-1 = <&spi_5_sleep>;
|
||
|
|
clock-names = "iface_clk", "core_clk";
|
||
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||
|
|
<&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spi_6: spi@7af5000 { /* BLSP2 QUP0 */
|
||
|
|
compatible = "qcom,spi-qup-v2";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg-names = "spi_physical", "spi_bam_physical";
|
||
|
|
reg = <0x7af5000 0x600>,
|
||
|
|
<0x7ac4000 0x17000>;
|
||
|
|
interrupt-names = "spi_irq", "spi_bam_irq";
|
||
|
|
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,use-bam;
|
||
|
|
qcom,ver-reg-exists;
|
||
|
|
qcom,bam-consumer-pipe-index = <2>;
|
||
|
|
qcom,bam-producer-pipe-index = <3>;
|
||
|
|
interconnect-names = "blsp-ddr";
|
||
|
|
interconnects = <&pc_noc MASTER_BLSP_2 &bimc SLAVE_EBI_CH0>;
|
||
|
|
qcom,use-pinctrl;
|
||
|
|
pinctrl-names = "spi_default", "spi_sleep";
|
||
|
|
pinctrl-0 = <&spi_6_active>;
|
||
|
|
pinctrl-1 = <&spi_6_sleep>;
|
||
|
|
clock-names = "iface_clk", "core_clk";
|
||
|
|
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
|
||
|
|
<&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
blsp1_uart1_hs: uart@78af000 { /* BLSP1 UART0 */
|
||
|
|
compatible = "qcom,msm-hsuart-v14";
|
||
|
|
reg = <0x78af000 0x200>,
|
||
|
|
<0x7884000 0x25000>;
|
||
|
|
reg-names = "core_mem", "bam_mem";
|
||
|
|
interrupts-extended = <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&intc GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&tlmm 31 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <0>;
|
||
|
|
qcom,inject-rx-on-wakeup;
|
||
|
|
qcom,rx-char-to-inject = <0xfd>;
|
||
|
|
qcom,bam-tx-ep-pipe-index = <0>;
|
||
|
|
qcom,bam-rx-ep-pipe-index = <1>;
|
||
|
|
interconnect-names = "blsp-ddr";
|
||
|
|
interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
clock-names = "core_clk", "iface_clk";
|
||
|
|
clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>,
|
||
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
||
|
|
pinctrl-names = "sleep", "default";
|
||
|
|
pinctrl-0 = <&blsp1_uart1_sleep>;
|
||
|
|
pinctrl-1 = <&blsp1_uart1_active>;
|
||
|
|
qcom,msm-bus,name = "buart1";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<86 512 0 0>,
|
||
|
|
<86 512 500 800>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp1_uart2_hs: uart@78b0000{ /* BLSP1 UART1 */
|
||
|
|
compatible = "qcom,msm-hsuart-v14";
|
||
|
|
reg = <0x78b0000 0x200>,
|
||
|
|
<0x7884000 0x25000>;
|
||
|
|
reg-names = "core_mem", "bam_mem";
|
||
|
|
interrupts-extended = <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&intc GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&tlmm 23 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <0>;
|
||
|
|
qcom,inject-rx-on-wakeup;
|
||
|
|
qcom,rx-char-to-inject = <0xfd>;
|
||
|
|
qcom,bam-tx-ep-pipe-index = <2>;
|
||
|
|
qcom,bam-rx-ep-pipe-index = <3>;
|
||
|
|
interconnect-names = "blsp-ddr";
|
||
|
|
interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
clock-names = "core_clk", "iface_clk";
|
||
|
|
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
|
||
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
||
|
|
pinctrl-names = "sleep", "default";
|
||
|
|
pinctrl-0 = <&blsp1_uart2_sleep>;
|
||
|
|
pinctrl-1 = <&blsp1_uart2_active>;
|
||
|
|
qcom,msm-bus,name = "buart2";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<86 512 0 0>,
|
||
|
|
<86 512 500 800>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp1_uart3_hs: uart@78b1000 { /* BLSP1 UART2 */
|
||
|
|
compatible = "qcom,msm-hsuart-v14";
|
||
|
|
reg = <0x78b1000 0x200>,
|
||
|
|
<0x7884000 0x25000>;
|
||
|
|
reg-names = "core_mem", "bam_mem";
|
||
|
|
interrupts-extended = <&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&intc GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&tlmm 18 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <0>;
|
||
|
|
qcom,inject-rx-on-wakeup;
|
||
|
|
qcom,rx-char-to-inject = <0xfd>;
|
||
|
|
qcom,bam-tx-ep-pipe-index = <4>;
|
||
|
|
qcom,bam-rx-ep-pipe-index = <5>;
|
||
|
|
interconnect-names = "blsp-ddr";
|
||
|
|
interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
clock-names = "core_clk", "iface_clk";
|
||
|
|
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
||
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
||
|
|
pinctrl-names = "sleep", "default";
|
||
|
|
pinctrl-0 = <&blsp1_uart3_sleep>;
|
||
|
|
pinctrl-1 = <&blsp1_uart3_active>;
|
||
|
|
qcom,msm-bus,name = "buart3";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<86 512 0 0>,
|
||
|
|
<86 512 500 800>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp1_uart4_hs: uart@78b2000 { /* BLSP1 UART3 */
|
||
|
|
compatible = "qcom,msm-hsuart-v14";
|
||
|
|
reg = <0x78b2000 0x200>,
|
||
|
|
<0x7884000 0x25000>;
|
||
|
|
reg-names = "core_mem", "bam_mem";
|
||
|
|
interrupts-extended = <&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&intc GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&tlmm 83 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <0>;
|
||
|
|
qcom,inject-rx-on-wakeup;
|
||
|
|
qcom,rx-char-to-inject = <0xfd>;
|
||
|
|
qcom,bam-tx-ep-pipe-index = <6>;
|
||
|
|
qcom,bam-rx-ep-pipe-index = <7>;
|
||
|
|
interconnect-names = "blsp-ddr";
|
||
|
|
interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
clock-names = "core_clk", "iface_clk";
|
||
|
|
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
|
||
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
||
|
|
pinctrl-names = "sleep", "default", "shutdown", "active";
|
||
|
|
pinctrl-0 = <&blsp1_uart4_tx_sleep>,
|
||
|
|
<&blsp1_uart4_rxcts_sleep>, <&blsp1_uart4_rfr_sleep>;
|
||
|
|
pinctrl-1 = <&blsp1_uart4_tx_sleep>,
|
||
|
|
<&blsp1_uart4_rxcts_sleep>, <&blsp1_uart4_rfr_sleep>;
|
||
|
|
pinctrl-2 = <&blsp1_uart4_tx_sleep>,
|
||
|
|
<&blsp1_uart4_rxcts_sleep>, <&blsp1_uart4_rfr_sleep>;
|
||
|
|
pinctrl-3 = <&blsp1_uart4_tx_active>,
|
||
|
|
<&blsp1_uart4_rxcts_active>, <&blsp1_uart4_rfr_active>;
|
||
|
|
qcom,msm-bus,name = "buart4";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<86 512 0 0>,
|
||
|
|
<86 512 500 800>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp2_uart1_hs: uart@7aef000 { /* BLSP2 UART0 */
|
||
|
|
compatible = "qcom,msm-hsuart-v14";
|
||
|
|
reg = <0x7aef000 0x200>,
|
||
|
|
<0x7ac4000 0x17000>;
|
||
|
|
reg-names = "core_mem", "bam_mem";
|
||
|
|
interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&tlmm 27 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <0>;
|
||
|
|
qcom,inject-rx-on-wakeup;
|
||
|
|
qcom,rx-char-to-inject = <0xfd>;
|
||
|
|
qcom,bam-tx-ep-pipe-index = <0>;
|
||
|
|
qcom,bam-rx-ep-pipe-index = <1>;
|
||
|
|
interconnect-names = "blsp-ddr";
|
||
|
|
interconnects = <&pc_noc MASTER_BLSP_2 &bimc SLAVE_EBI_CH0>;
|
||
|
|
clock-names = "core_clk", "iface_clk";
|
||
|
|
clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>,
|
||
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
||
|
|
pinctrl-names = "sleep", "default";
|
||
|
|
pinctrl-0 = <&blsp2_uart1_sleep>;
|
||
|
|
pinctrl-1 = <&blsp2_uart1_active>;
|
||
|
|
qcom,msm-bus,name = "buart5";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<84 512 0 0>,
|
||
|
|
<84 512 500 800>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|