Rtwo/kernel/motorola/sm8550-devicetrees/qcom/qrb3165-cpu.dtsi

/ {
	/delete-node/ cpus;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_0>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
				      compatible = "arm,arch-cache";
				      cache-level = <3>;
				};
			};

			L1_I_0: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_0: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_1>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			L2_1: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L1_I_100: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_100: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_2>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			L2_2: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L2_I_100: l2-icache {
				compatible = "arm,arch-cache";
			};

			L2_D_100: l2-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU3: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x400>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_4>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			capacity-dmips-mhz = <1894>;
			dynamic-power-coefficient = <514>;
			#cooling-cells = <2>;
			L2_4: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L1_I_400: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_400: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU4: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x500>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF>;
			power-domains = <&CPU_PD4>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_5>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			capacity-dmips-mhz = <1894>;
			dynamic-power-coefficient = <514>;
			L2_5: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L1_I_500: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_500: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU5: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x600>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF>;
			power-domains = <&CPU_PD5>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_6>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			capacity-dmips-mhz = <1894>;
			dynamic-power-coefficient = <514>;
			L2_6: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L1_I_600: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_600: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU3>;
				};

				core1 {
					cpu = <&CPU4>;
				};

				core2 {
					cpu = <&CPU5>;
				};
			};
		};
	};
};

&soc {
	/delete-node/ dsu_pmu@0;
	/delete-node/ jtagmm@7340000;
	/delete-node/ cti@7320000;
	/delete-node/ cti@7720000;
	/delete-node/ etm@7340000;
	/delete-node/ etm@7740000;
	/delete-node/ qcom,chd;

	psci {
		/delete-node/ cpu-pd6;
		/delete-node/ cpu-pd7;
	};

	dsu_pmu@0 {
		compatible = "arm,dsu-pmu";
		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
		cpus = <&CPU0>, <&CPU1>,<&CPU2>,
			<&CPU3>, <&CPU4>, <&CPU5>;
	};

	cti_cpu4: cti@7420000 {
		cpu = <&CPU3>;
	};

	cti_cpu5: cti@7520000 {
		cpu = <&CPU4>;
	};

	cti_cpu6: cti@7620000 {
		cpu = <&CPU5>;
	};

	etm4: etm@7440000 {
		cpu = <&CPU3>;
	};

	etm5: etm@7540000 {
		cpu = <&CPU4>;
	};

	etm6: etm@7640000 {
		cpu = <&CPU5>;
	};

	funnel_apss: funnel@7800000 {
		in-ports {
			/delete-node/ port@4;
			/delete-node/ port@8;
		};
	};

	qcom,chd {
		compatible = "qcom,core-hang-detect";
		label = "core";
		qcom,chd-percpu-info = <&CPU0 0x18000058 0x18000060>,
					<&CPU1 0x18010058 0x18010060>,
					<&CPU2 0x18020058 0x18020060>,
					<&CPU3 0x18030058 0x18030060>,
					<&CPU4 0x18040058 0x18040060>,
					<&CPU5 0x18050058 0x18050060>;
	};
};

&cpufreq_hw {
	/delete-node/ cpu7-notify;
};

&qcom_memlat {
	ddr {
		silver {
			/delete-property/  qcom,cpulist;
			qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
		};

		gold {
			/delete-property/  qcom,cpulist;
			qcom,cpulist = <&CPU3 &CPU4 &CPU5>;
		};

		gold-compute {
			/delete-property/  qcom,cpulist;
			qcom,cpulist = <&CPU3 &CPU4 &CPU5>;
		};
	};

	llcc {
		silver {
			/delete-property/  qcom,cpulist;
			qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
		};

		gold {
			/delete-property/  qcom,cpulist;
			qcom,cpulist = <&CPU3 &CPU4 &CPU5>;
		};
	};

	l3 {
		/delete-node/ prime;
		silver {
			/delete-property/  qcom,cpulist;
			qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
		};

		gold {
			/delete-property/  qcom,cpulist;
			qcom,cpulist = <&CPU3 &CPU4 &CPU5>;
		};
	};

	ddrqos {
		ddrqos_gold_lat: gold {
			/delete-property/  qcom,cpulist;
			qcom,cpulist = <&CPU3 &CPU4 &CPU5>;
		};
	};
};

&soc {

	qcom,cpu-pause {
		/delete-node/ cpu6-pause;
		/delete-node/ cpu7-pause;
		/delete-node/ pause-cpu6;
		/delete-node/ pause-cpu7;
	};

	qcom,cpu-hotplug {
		/delete-node/ cpu6-hotplug;
		/delete-node/ cpu7-hotplug;
	};

	qcom,cpufreq-cdev {
		compatible = "qcom,cpufreq-cdev";
		cpu-cluster0 {
			qcom,cpus = <&CPU0 &CPU1 &CPU2>;
		};

		cpu-cluster1 {
			qcom,cpus = <&CPU3 &CPU4 &CPU5>;
		};

		/delete-node/ cpu-cluster2;
	};
};

&thermal_zones {

	cpu-1-0 {
		cooling-maps {
			/delete-node/ cpufreq_cdev;
		};
	};

	cpu-1-1 {
		cooling-maps {
			/delete-node/ cpufreq_cdev;
		};
	};

	cpu-1-2 {
		cooling-maps {
			/delete-node/ cpufreq_cdev;
			/delete-node/ cpu12_cdev;
		};
	};

	cpu-1-3 {
		cooling-maps {
			/delete-node/ cpufreq_cdev;
			/delete-node/ cpu13_cdev;
		};
	};

	cpu-1-4 {
		cooling-maps {
			/delete-node/ cpufreq_cdev;
		};
	};

	cpu-1-5 {
		cooling-maps {
			/delete-node/ cpufreq_cdev;
		};
	};

	cpu-1-6 {
		cooling-maps {
			/delete-node/ cpufreq_cdev;
			/delete-node/ cpu16_cdev;
		};
	};

	cpu-1-7 {
		cooling-maps {
			/delete-node/ cpufreq_cdev;
			/delete-node/ cpu17_cdev;
		};
	};

	ddr {
		cooling-maps {
			/delete-node/ cpu_cdev7;
			cpu_cdev4 {
			/delete-property/  cooling-device;
			cooling-device = <&CPU3 THERMAL_NO_LIMIT
					THERMAL_NO_LIMIT>;
			};
		};
	};
};