244 lines
5.9 KiB
Text
244 lines
5.9 KiB
Text
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#include "sdmshrike-v2.dtsi"
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#include "sa8195-pmic.dtsi"
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#include "sa8195p-pcie.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SA8195P";
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qcom,msm-name = "SA8195P";
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qcom,msm-id = <405 0x20000>;
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aliases {
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hsuart0 = &qupv3_se17_4uart;
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};
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};
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&soc {
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qfprom: qfprom@780130 {
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compatible = "qcom,qfprom";
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reg = <0x00780130 0x4>;
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#address-cells = <1>;
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#size-cells = <1>;
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read-only;
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ranges;
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gpu_speed_bin: gpu_speed_bin@2 {
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reg = <0x2 0x2>;
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bits = <4 8>;
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};
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};
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hsi2s: qcom,hsi2s {
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compatible = "qcom,sa8195-hsi2s", "qcom,hsi2s";
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number-of-interfaces = <3>;
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reg = <0x172C0000 0x28000>,
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<0x17080000 0xE000>;
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reg-names = "lpa_if", "lpass_tcsr";
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interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
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number-of-rate-detectors = <2>;
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rate-detector-interfaces = <0 1>;
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iommus = <&apps_smmu 0x1B5C 0x1>,
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<&apps_smmu 0x1B5E 0x0>;
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qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>;
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sdr0: qcom,hs0_i2s {
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compatible = "qcom,hsi2s-interface";
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minor-number = <0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&hs1_i2s_mclk_active &hs1_i2s_sck_active
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&hs1_i2s_ws_active &hs1_i2s_data0_active
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&hs1_i2s_data1_active>;
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pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep
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&hs1_i2s_ws_sleep &hs1_i2s_data0_sleep
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&hs1_i2s_data1_sleep>;
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bit-clock-hz = <12288000>;
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data-buffer-ms = <10>;
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bit-depth = <32>;
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spkr-channel-count = <2>;
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mic-channel-count = <2>;
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pcm-rate = <2>;
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pcm-sync-src = <0>;
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aux-mode = <0>;
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rpcm-width = <1>;
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tpcm-width = <1>;
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enable-tdm = <1>;
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tdm-rate = <32>;
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tdm-rpcm-width = <16>;
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tdm-tpcm-width = <16>;
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tdm-sync-delay = <2>;
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tdm-inv-sync = <0>;
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pcm-lane-config = <1>;
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};
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sdr1: qcom,hs1_i2s {
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compatible = "qcom,hsi2s-interface";
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minor-number = <1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&hs2_i2s_mclk_active &hs2_i2s_sck_active
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&hs2_i2s_ws_active &hs2_i2s_data0_active
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&hs2_i2s_data1_active>;
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pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep
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&hs2_i2s_ws_sleep &hs2_i2s_data0_sleep
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&hs2_i2s_data1_sleep>;
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bit-clock-hz = <12288000>;
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data-buffer-ms = <10>;
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bit-depth = <32>;
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spkr-channel-count = <2>;
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mic-channel-count = <2>;
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pcm-rate = <2>;
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pcm-sync-src = <0>;
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aux-mode = <0>;
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rpcm-width = <1>;
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tpcm-width = <1>;
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enable-tdm = <1>;
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tdm-rate = <32>;
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tdm-rpcm-width = <16>;
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tdm-tpcm-width = <16>;
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tdm-sync-delay = <2>;
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tdm-inv-sync = <0>;
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pcm-lane-config = <1>;
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};
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sdr2: qcom,hs2_i2s {
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compatible = "qcom,hsi2s-interface";
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minor-number = <2>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&hs3_i2s_mclk_active &hs3_i2s_sck_active
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&hs3_i2s_ws_active &hs3_i2s_data0_active
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&hs3_i2s_data1_active>;
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pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep
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&hs3_i2s_ws_sleep &hs3_i2s_data0_sleep
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&hs3_i2s_data1_sleep>;
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bit-clock-hz = <12288000>;
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data-buffer-ms = <10>;
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bit-depth = <32>;
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spkr-channel-count = <2>;
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mic-channel-count = <2>;
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pcm-rate = <2>;
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pcm-sync-src = <0>;
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aux-mode = <0>;
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rpcm-width = <1>;
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tpcm-width = <1>;
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enable-tdm = <1>;
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tdm-rate = <32>;
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tdm-rpcm-width = <16>;
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tdm-tpcm-width = <16>;
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tdm-sync-delay = <2>;
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tdm-inv-sync = <0>;
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pcm-lane-config = <1>;
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};
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};
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};
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&scc {
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vdd_scc_cx-supply = <&VDD_SCC_CX_LEVEL>;
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status = "ok";
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};
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&sdhc_2 {
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vdd-supply = <&pm8195_1_l10>;
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qcom,vdd-voltage-level = <2950000 2960000>;
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qcom,vdd-current-level = <200 800000>;
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vdd-io-supply = <&pm8195_1_l2>;
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qcom,vdd-io-voltage-level = <1808000 2960000>;
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qcom,vdd-io-current-level = <200 22000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc2_on>;
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pinctrl-1 = <&sdc2_off>;
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cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>;
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status = "ok";
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};
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qmp-v4";
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vdda-phy-supply = <&pm8195_3_l5>;
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vdda-pll-supply = <&pm8195_1_l9>;
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vdda-phy-max-microamp = <138000>;
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vdda-pll-max-microamp = <65100>;
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status = "ok";
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};
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&ufshc_mem {
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vdd-hba-supply = <&ufs_phy_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm8195_1_l17>;
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vccq-supply = <&pm8195_2_l5>;
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//vccq2-supply = <&pm8195_s4>;
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vcc-max-microamp = <750000>;
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vccq-max-microamp = <750000>;
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vccq2-max-microamp = <750000>;
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nvmem-cells = <&ufs_dev>;
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nvmem-cell-names = "ufs_dev";
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limit-rate-ufs3;
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qcom,vddp-ref-clk-supply = <&pm8195_2_l5>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vccq-parent-supply = <&pm8195_1_s2>;
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qcom,vccq-parent-max-microamp = <210000>;
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/* Disable Write Booster Feature */
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qcom,disable-wb-support;
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status= "ok";
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};
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&ufs2phy_mem {
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compatible = "qcom,ufs-phy-qmp-v4";
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vdda-phy-supply = <&pm8195_3_l5>;
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vdda-pll-supply = <&pm8195_1_l9>;
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vdda-phy-max-microamp = <138000>;
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vdda-pll-max-microamp = <65100>;
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status = "ok";
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};
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&ufshc2_mem {
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vdd-hba-supply = <&ufs_card_2_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm8195_3_l10>;
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vccq-supply = <&pm8195_1_l11>;
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vccq2-supply = <&pm8195_3_l7>;
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vcc-max-microamp = <750000>;
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vccq-max-microamp = <750000>;
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vccq2-max-microamp = <750000>;
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qcom,vddp-ref-clk-supply = <&pm8195_2_l5>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vccq-parent-supply = <&pm8195_1_s2>;
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qcom,vccq-parent-max-microamp = <210000>;
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/* Disable Write Booster Feature 2nd UFS */
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qcom,disable-wb-support;
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status= "ok";
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};
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/* Add CNSS power ctrl nodes specific to SA8195 */
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&soc {
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/* PWR_CTR2_VDD_1P8 supply */
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vreg_conn_1p8: vreg_conn_1p8 {
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compatible = "regulator-fixed";
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regulator-name = "vreg_conn_1p8";
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pinctrl-names = "default";
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pinctrl-0 = <&conn_power_1p8_active>;
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startup-delay-us = <4000>;
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enable-active-high;
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gpio = <&tlmm 173 0>;
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};
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/* PWR_CTR1_VDD_PA supply */
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vreg_conn_pa: vreg_conn_pa {
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compatible = "regulator-fixed";
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regulator-name = "vreg_conn_pa";
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pinctrl-names = "default";
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pinctrl-0 = <&conn_power_pa_active>;
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startup-delay-us = <4000>;
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enable-active-high;
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gpio = <&tlmm 174 0>;
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};
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};
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#include "sdmshrike-coresight.dtsi"
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