786 lines
23 KiB
Text
786 lines
23 KiB
Text
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&soc {
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gpi_dma0: qcom,gpi-dma@0x800000 {
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#dma-cells = <5>;
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compatible = "qcom,gpi-dma";
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reg = <0x800000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>,
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<0 245 IRQ_TYPE_LEVEL_HIGH>,
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<0 246 IRQ_TYPE_LEVEL_HIGH>,
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<0 247 IRQ_TYPE_LEVEL_HIGH>,
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<0 248 IRQ_TYPE_LEVEL_HIGH>,
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<0 249 IRQ_TYPE_LEVEL_HIGH>,
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<0 250 IRQ_TYPE_LEVEL_HIGH>,
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<0 251 IRQ_TYPE_LEVEL_HIGH>,
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<0 252 IRQ_TYPE_LEVEL_HIGH>,
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<0 253 IRQ_TYPE_LEVEL_HIGH>,
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<0 254 IRQ_TYPE_LEVEL_HIGH>,
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<0 255 IRQ_TYPE_LEVEL_HIGH>,
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<0 256 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <13>;
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qcom,gpii-mask = <0xfa>;
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qcom,ev-factor = <2>;
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iommus = <&apps_smmu 0x0016 0x0>;
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qcom,smmu-cfg = <0x1>;
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qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
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status = "ok";
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};
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gpi_dma1: qcom,gpi-dma@0xa00000 {
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#dma-cells = <5>;
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compatible = "qcom,gpi-dma";
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reg = <0xa00000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <0 279 IRQ_TYPE_LEVEL_HIGH>,
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<0 280 IRQ_TYPE_LEVEL_HIGH>,
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<0 281 IRQ_TYPE_LEVEL_HIGH>,
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<0 282 IRQ_TYPE_LEVEL_HIGH>,
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<0 283 IRQ_TYPE_LEVEL_HIGH>,
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<0 284 IRQ_TYPE_LEVEL_HIGH>,
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<0 293 IRQ_TYPE_LEVEL_HIGH>,
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<0 294 IRQ_TYPE_LEVEL_HIGH>,
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<0 295 IRQ_TYPE_LEVEL_HIGH>,
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<0 296 IRQ_TYPE_LEVEL_HIGH>,
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<0 297 IRQ_TYPE_LEVEL_HIGH>,
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<0 298 IRQ_TYPE_LEVEL_HIGH>,
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<0 299 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <13>;
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qcom,gpii-mask = <0xfa>;
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qcom,ev-factor = <2>;
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qcom,smmu-cfg = <0x1>;
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qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
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iommus = <&apps_smmu 0x06d6 0x0>;
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status = "ok";
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};
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/* QUPv3 South instances */
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qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x8c0000 0x6000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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iommus = <&apps_smmu 0x003 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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ranges;
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status = "ok";
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/*
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* HS UART instances. HS UART usecases can be supported on these
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* instances only.
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*/
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qupv3_se6_4uart: qcom,qup_uart@0x898000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x898000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
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<&qupv3_se6_tx>;
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pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
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<&qupv3_se6_tx>;
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interrupts-extended = <&pdc GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 48 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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qcom,wakeup-byte = <0xFD>;
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qcom,wrapper-core = <&qupv3_0>;
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};
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qupv3_se7_4uart: qcom,qup_uart@0x89c000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x89c000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se7_4uart_active>;
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pinctrl-1 = <&qupv3_se7_4uart_sleep>;
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interrupts-extended = <&pdc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 96 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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qcom,wakeup-byte = <0xFD>;
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qcom,wrapper-core = <&qupv3_0>;
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};
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/* I2C */
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qupv3_se0_i2c: i2c@880000 {
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compatible = "qcom,i2c-geni";
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reg = <0x880000 0x4000>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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dmas = <&gpi_dma0 0 0 3 64 0>,
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<&gpi_dma0 1 0 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se1_i2c: i2c@884000 {
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compatible = "qcom,i2c-geni";
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reg = <0x884000 0x4000>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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dmas = <&gpi_dma0 0 1 3 64 0>,
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<&gpi_dma0 1 1 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_i2c_active>;
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pinctrl-1 = <&qupv3_se1_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se2_i2c: i2c@888000 {
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compatible = "qcom,i2c-geni";
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reg = <0x888000 0x4000>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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dmas = <&gpi_dma0 0 2 3 64 0>,
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<&gpi_dma0 1 2 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se3_i2c: i2c@88c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x88c000 0x4000>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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dmas = <&gpi_dma0 0 3 3 64 0>,
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<&gpi_dma0 1 3 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_i2c_active>;
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pinctrl-1 = <&qupv3_se3_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se4_i2c: i2c@890000 {
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compatible = "qcom,i2c-geni";
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reg = <0x890000 0x4000>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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dmas = <&gpi_dma0 0 4 3 64 0>,
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<&gpi_dma0 1 4 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_i2c_active>;
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pinctrl-1 = <&qupv3_se4_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se5_i2c: i2c@894000 {
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compatible = "qcom,i2c-geni";
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reg = <0x894000 0x4000>;
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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dmas = <&gpi_dma0 0 5 3 64 0>,
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<&gpi_dma0 1 5 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_i2c_active>;
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pinctrl-1 = <&qupv3_se5_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se6_i2c: i2c@898000 {
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compatible = "qcom,i2c-geni";
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reg = <0x898000 0x4000>;
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
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dmas = <&gpi_dma0 0 6 3 64 0>,
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<&gpi_dma0 1 6 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_i2c_active>;
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pinctrl-1 = <&qupv3_se6_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se7_i2c: i2c@89c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x89c000 0x4000>;
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interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
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dmas = <&gpi_dma0 0 7 3 64 0>,
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<&gpi_dma0 1 7 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se7_i2c_active>;
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pinctrl-1 = <&qupv3_se7_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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/* SPI */
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qupv3_se0_spi: spi@880000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x880000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_spi_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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dmas = <&gpi_dma0 0 0 1 64 0>,
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<&gpi_dma0 1 0 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se1_spi: spi@884000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x884000 0x4000>;
|
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reg-names = "se_phys";
|
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
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pinctrl-names = "default", "sleep";
|
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|
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pinctrl-0 = <&qupv3_se1_spi_active>;
|
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|
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pinctrl-1 = <&qupv3_se1_spi_sleep>;
|
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
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|
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spi-max-frequency = <50000000>;
|
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|
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qcom,wrapper-core = <&qupv3_0>;
|
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dmas = <&gpi_dma0 0 1 1 64 0>,
|
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<&gpi_dma0 1 1 1 64 0>;
|
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dma-names = "tx", "rx";
|
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status = "disabled";
|
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};
|
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|
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qupv3_se2_spi: spi@888000 {
|
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|
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compatible = "qcom,spi-geni";
|
||
|
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#address-cells = <1>;
|
||
|
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#size-cells = <0>;
|
||
|
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reg = <0x888000 0x4000>;
|
||
|
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reg-names = "se_phys";
|
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|
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clock-names = "se-clk";
|
||
|
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||
|
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pinctrl-names = "default", "sleep";
|
||
|
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pinctrl-0 = <&qupv3_se2_spi_active>;
|
||
|
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pinctrl-1 = <&qupv3_se2_spi_sleep>;
|
||
|
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
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spi-max-frequency = <50000000>;
|
||
|
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qcom,wrapper-core = <&qupv3_0>;
|
||
|
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dmas = <&gpi_dma0 0 2 1 64 0>,
|
||
|
|
<&gpi_dma0 1 2 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se3_spi: spi@88c000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0x88c000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se3_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se3_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_0>;
|
||
|
|
dmas = <&gpi_dma0 0 3 1 64 0>,
|
||
|
|
<&gpi_dma0 1 3 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se4_spi: spi@890000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0x890000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se4_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se4_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_0>;
|
||
|
|
dmas = <&gpi_dma0 0 4 1 64 0>,
|
||
|
|
<&gpi_dma0 1 4 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se5_spi: spi@894000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0x894000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se5_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se5_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_0>;
|
||
|
|
dmas = <&gpi_dma0 0 5 1 64 0>,
|
||
|
|
<&gpi_dma0 1 5 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se6_spi: spi@898000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0x898000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se6_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se6_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_0>;
|
||
|
|
dmas = <&gpi_dma0 0 6 1 64 0>,
|
||
|
|
<&gpi_dma0 1 6 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se7_spi: spi@89c000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0x89c000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se7_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se7_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_0>;
|
||
|
|
dmas = <&gpi_dma0 0 7 1 64 0>,
|
||
|
|
<&gpi_dma0 1 7 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* QUPv3 North Instances */
|
||
|
|
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
|
||
|
|
compatible = "qcom,geni-se-qup";
|
||
|
|
reg = <0xac0000 0x6000>;
|
||
|
|
clock-names = "m-ahb", "s-ahb";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||
|
|
iommus = <&apps_smmu 0x6c3 0x0>;
|
||
|
|
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
||
|
|
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||
|
|
qcom,iommu-dma = "fastmap";
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
/* 2-wire UART */
|
||
|
|
|
||
|
|
/* Debug UART Instance for CDP/MTP platform */
|
||
|
|
qupv3_se9_2uart: qcom,qup_uart@0xa84000 {
|
||
|
|
compatible = "qcom,geni-debug-uart";
|
||
|
|
reg = <0xa84000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se9_2uart_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se9_2uart_sleep>;
|
||
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Debug UART Instance for RUMI platform */
|
||
|
|
qupv3_se10_2uart: qcom,qup_uart@0xa88000 {
|
||
|
|
compatible = "qcom,geni-debug-uart";
|
||
|
|
reg = <0xa88000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se10_2uart_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se10_2uart_sleep>;
|
||
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Debug UART Instance for CDP/MTP platform on SDM670 */
|
||
|
|
qupv3_se12_2uart: qcom,qup_uart@0xa90000 {
|
||
|
|
compatible = "qcom,geni-debug-uart";
|
||
|
|
reg = <0xa90000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se12_2uart_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se12_2uart_sleep>;
|
||
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
status = "ok";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* I2C */
|
||
|
|
qupv3_se8_i2c: i2c@a80000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0xa80000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||
|
|
dmas = <&gpi_dma1 0 0 3 64 0>,
|
||
|
|
<&gpi_dma1 1 0 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se8_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se9_i2c: i2c@a84000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0xa84000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||
|
|
dmas = <&gpi_dma1 0 1 3 64 0>,
|
||
|
|
<&gpi_dma1 1 1 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se9_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se10_i2c: i2c@a88000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0xa88000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||
|
|
dmas = <&gpi_dma1 0 2 3 64 0>,
|
||
|
|
<&gpi_dma1 1 2 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se10_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se11_i2c: i2c@a8c000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0xa8c000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||
|
|
dmas = <&gpi_dma1 0 3 3 64 0>,
|
||
|
|
<&gpi_dma1 1 3 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se11_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se12_i2c: i2c@a90000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0xa90000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||
|
|
dmas = <&gpi_dma1 0 4 3 64 0>,
|
||
|
|
<&gpi_dma1 1 4 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se12_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se12_i2c_sleep>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se13_i2c: i2c@a94000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0xa94000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||
|
|
dmas = <&gpi_dma1 0 5 3 64 0>,
|
||
|
|
<&gpi_dma1 1 5 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se13_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se13_i2c_sleep>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se14_i2c: i2c@a98000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0xa98000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
||
|
|
dmas = <&gpi_dma1 0 6 3 64 0>,
|
||
|
|
<&gpi_dma1 1 6 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se14_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se14_i2c_sleep>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se15_i2c: i2c@a9c000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0xa9c000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
||
|
|
dmas = <&gpi_dma1 0 7 3 64 0>,
|
||
|
|
<&gpi_dma1 1 7 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se15_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se15_i2c_sleep>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* SPI */
|
||
|
|
qupv3_se8_spi: spi@a80000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0xa80000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se8_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se8_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
dmas = <&gpi_dma1 0 0 1 64 0>,
|
||
|
|
<&gpi_dma1 1 0 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se9_spi: spi@a84000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0xa84000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se9_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se9_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
dmas = <&gpi_dma1 0 1 1 64 0>,
|
||
|
|
<&gpi_dma1 1 1 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se10_spi: spi@a88000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0xa88000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se10_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se10_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
dmas = <&gpi_dma1 0 2 1 64 0>,
|
||
|
|
<&gpi_dma1 1 2 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se11_spi: spi@a8c000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0xa8c000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se11_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se11_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
dmas = <&gpi_dma1 0 3 1 64 0>,
|
||
|
|
<&gpi_dma1 1 3 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se12_spi: spi@a90000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0xa90000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se12_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se12_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
dmas = <&gpi_dma1 0 4 1 64 0>,
|
||
|
|
<&gpi_dma1 1 4 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se13_spi: spi@a94000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0xa94000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se13_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se13_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
dmas = <&gpi_dma1 0 5 1 64 0>,
|
||
|
|
<&gpi_dma1 1 5 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se14_spi: spi@a98000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0xa98000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se14_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se14_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
dmas = <&gpi_dma1 0 6 1 64 0>,
|
||
|
|
<&gpi_dma1 1 6 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se15_spi: spi@a9c000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0xa9c000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se15_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se15_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
dmas = <&gpi_dma1 0 7 1 64 0>,
|
||
|
|
<&gpi_dma1 1 7 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|