402 lines
14 KiB
Text
402 lines
14 KiB
Text
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&soc {
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/* QUPv3 SE Instances
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* Qup0 0: SE 0
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* Qup0 1: SE 1
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* Qup0 2: SE 2
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* Qup0 3: SE 3
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* Qup0 4: SE 4
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* Qup0 5: SE 5
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* Qup0 6: SE 6
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* Qup0 7: SE 7
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* Qup0 8: SE 8
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*/
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/* GPI Instance */
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gpi_dma0: qcom,gpi-dma@900000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x900000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0xf6 0x0>;
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qcom,max-num-gpii = <12>;
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interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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qcom,gpii-mask = <0x7f>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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qcom,gpi-ee-offset = <0x10000>;
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dma-coherent;
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status = "ok";
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};
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/* QUPv3_0 wrapper instance */
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qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x9c0000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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iommus = <&apps_smmu 0xe3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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dma-coherent;
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ranges;
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status = "ok";
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/* PORed Debug UART Instance */
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qupv3_se1_2uart: qcom,qup_uart@984000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x984000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_2uart_tx_active>, <&qupv3_se1_2uart_rx_active>;
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pinctrl-1 = <&qupv3_se1_2uart_sleep>;
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status = "disabled";
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};
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/* HS UART Instance */
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qupv3_se3_4uart: qcom,qup_uart@98c000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x98c000 0x4000>;
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reg-names = "se_phys";
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interrupts-extended = <&intc GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 55 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "active", "sleep", "shutdown";
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pinctrl-0 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>,
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<&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>;
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pinctrl-1 = <&qupv3_se3_cts>, <&qupv3_se3_rts>,
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<&qupv3_se3_tx>, <&qupv3_se3_rx>;
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pinctrl-2 = <&qupv3_se3_cts>, <&qupv3_se3_rts>,
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<&qupv3_se3_tx>, <&qupv3_se3_default_rx>;
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pinctrl-3 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>,
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<&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>;
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qcom,wakeup-byte = <0xFD>;
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status = "disabled";
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};
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qupv3_se0_i2c: i2c@980000 {
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compatible = "qcom,i2c-geni";
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reg = <0x980000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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dmas = <&gpi_dma0 0 0 3 64 0>,
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<&gpi_dma0 1 0 3 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se0_spi: spi@980000 {
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compatible = "qcom,spi-geni";
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reg = <0x980000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
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<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep>;
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dmas = <&gpi_dma0 0 0 1 64 0>,
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<&gpi_dma0 1 0 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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qupv3_se2_i2c: i2c@988000 {
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compatible = "qcom,i2c-geni";
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reg = <0x988000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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dmas = <&gpi_dma0 0 2 3 64 0>,
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<&gpi_dma0 1 2 3 64 0>;
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dma-names = "tx", "rx";
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qcom,shared;
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status = "disabled";
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};
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qupv3_se2_spi: spi@988000 {
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compatible = "qcom,spi-geni";
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reg = <0x988000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
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<&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
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pinctrl-1 = <&qupv3_se2_spi_sleep>;
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dmas = <&gpi_dma0 0 2 1 64 0>,
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<&gpi_dma0 1 2 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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qupv3_se3_i2c: i2c@98c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x98c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
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pinctrl-1 = <&qupv3_se3_i2c_sleep>;
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dmas = <&gpi_dma0 0 3 3 64 0>,
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<&gpi_dma0 1 3 3 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se3_spi: spi@98c000 {
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compatible = "qcom,spi-geni";
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reg = <0x98c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>,
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<&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>;
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pinctrl-1 = <&qupv3_se3_spi_sleep>;
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dmas = <&gpi_dma0 0 3 1 64 0>,
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<&gpi_dma0 1 3 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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/* CV2X UART1 Instance */
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qupv3_se4_2uart: qcom,qup_uart@990000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x990000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_2uart_tx_active>, <&qupv3_se4_2uart_rx_active>;
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pinctrl-1 = <&qupv3_se4_2uart_sleep>;
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status = "disabled";
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};
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qupv3_se5_i2c: i2c@994000 {
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compatible = "qcom,i2c-geni";
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reg = <0x994000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
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pinctrl-1 = <&qupv3_se5_i2c_sleep>;
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dmas = <&gpi_dma0 0 5 3 64 0>,
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<&gpi_dma0 1 5 3 64 0>;
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|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se6_i2c: i2c@998000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0x998000 0x4000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
||
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||
|
|
<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
|
||
|
|
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
|
||
|
|
dmas = <&gpi_dma0 0 6 3 64 0>,
|
||
|
|
<&gpi_dma0 1 6 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se6_spi: spi@998000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
reg = <0x998000 0x4000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
||
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||
|
|
<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
|
||
|
|
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
|
||
|
|
<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se6_spi_sleep>;
|
||
|
|
dmas = <&gpi_dma0 0 6 1 64 0>,
|
||
|
|
<&gpi_dma0 1 6 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se7_i2c: i2c@99c000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0x99c000 0x4000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
|
||
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||
|
|
<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
|
||
|
|
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se7_i2c_sleep>;
|
||
|
|
dmas = <&gpi_dma0 0 7 3 64 0>,
|
||
|
|
<&gpi_dma0 1 7 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se7_spi: spi@99c000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
reg = <0x99c000 0x4000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
|
||
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||
|
|
<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
|
||
|
|
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>,
|
||
|
|
<&qupv3_se7_spi_clk_active>, <&qupv3_se7_spi_cs_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se7_spi_sleep>;
|
||
|
|
dmas = <&gpi_dma0 0 7 1 64 0>,
|
||
|
|
<&gpi_dma0 1 7 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* CV2X UART2 Instance */
|
||
|
|
qupv3_se8_2uart: qcom,qup_uart@9a0000 {
|
||
|
|
compatible = "qcom,geni-debug-uart";
|
||
|
|
reg = <0x9a0000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clock-names = "se";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
|
||
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||
|
|
<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
|
||
|
|
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se8_2uart_tx_active>, <&qupv3_se8_2uart_rx_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se8_2uart_sleep>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|