738 lines
16 KiB
Text
738 lines
16 KiB
Text
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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model = "Qualcomm Technologies, Inc. SM6150";
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compatible = "qcom,sm6150";
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qcom,msm-name = "SM6150";
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qcom,msm-id = <355 0x0>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases {
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serial0 = &uart2;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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i-cache-size = <0x8000>;
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d-cache-size = <0x8000>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x100000>;
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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i-cache-size = <0x8000>;
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d-cache-size = <0x8000>;
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next-level-cache = <&L2_100>;
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L2_100: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
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power-domains = <&CPU_PD2>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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i-cache-size = <0x8000>;
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d-cache-size = <0x8000>;
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next-level-cache = <&L2_200>;
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L2_200: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
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power-domains = <&CPU_PD3>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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i-cache-size = <0x8000>;
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d-cache-size = <0x8000>;
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next-level-cache = <&L2_300>;
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L2_300: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
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power-domains = <&CPU_PD4>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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i-cache-size = <0x8000>;
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d-cache-size = <0x8000>;
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next-level-cache = <&L2_400>;
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L2_400: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
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power-domains = <&CPU_PD5>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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i-cache-size = <0x8000>;
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d-cache-size = <0x8000>;
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next-level-cache = <&L2_500>;
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L2_500: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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power-domains = <&CPU_PD6>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1740>;
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i-cache-size = <0x10000>;
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d-cache-size = <0x10000>;
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next-level-cache = <&L2_600>;
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#cooling-cells = <2>;
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L2_600: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x40000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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power-domains = <&CPU_PD7>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1740>;
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i-cache-size = <0x10000>;
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d-cache-size = <0x10000>;
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next-level-cache = <&L2_700>;
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L2_700: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x40000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU6>;
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};
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core1 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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idle-states {
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SILVER_OFF: silver-c3 { /* C3 */
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <549>;
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exit-latency-us = <901>;
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min-residency-us = <1774>;
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arm,psci-suspend-param = <0x40000003>;
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local-timer-stop;
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};
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SILVER_PLL_OFF: silver-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <702>;
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exit-latency-us = <915>;
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min-residency-us = <4001>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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GOLD_OFF: gold-c3 { /* C3 */
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <523>;
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exit-latency-us = <1244>;
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min-residency-us = <2207>;
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arm,psci-suspend-param = <0x40000003>;
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local-timer-stop;
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};
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GOLD_RAIL_OFF: gold-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <526>;
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exit-latency-us = <1854>;
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min-residency-us = <5555>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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CLUSTER_OFF: cluster-d4 { /* D4 */
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compatible = "domain-idle-state";
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idle-state-name = "llcc-off";
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entry-latency-us = <2752>;
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exit-latency-us = <3048>;
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min-residency-us = <6118>;
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arm,psci-suspend-param = <0x41000044>;
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};
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CX_RET: cx-ret { /* Cx Ret */
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compatible = "domain-idle-state";
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idle-state-name = "llcc-off";
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entry-latency-us = <3263>;
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exit-latency-us = <4562>;
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min-residency-us = <8467>;
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arm,psci-suspend-param = <0x41001344>;
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};
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APSS_OFF: cluster-e3 { /* AOSS sleep */
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compatible = "domain-idle-state";
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idle-state-name = "llcc-off";
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entry-latency-us = <3638>;
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exit-latency-us = <6562>;
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min-residency-us = <9826>;
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arm,psci-suspend-param = <0x4100b344>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: cpu-pd0 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD1: cpu-pd1 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD2: cpu-pd2 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD3: cpu-pd3 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD4: cpu-pd4 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD5: cpu-pd5 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD6: cpu-pd6 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD7: cpu-pd7 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CLUSTER_PD: cluster-pd {
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#power-domain-cells = <0>;
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domain-idle-states = <&CLUSTER_OFF &CX_RET &APSS_OFF>;
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};
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};
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chosen { };
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soc: soc { };
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firmware: firmware { };
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_region: hyp_region@85700000 {
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no-map;
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reg = <0x0 0x85700000 0x0 0x600000>;
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};
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xbl_aop_mem: xbl_aop_mem@85e00000 {
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no-map;
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reg = <0x0 0x85e00000 0x0 0x120000>;
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};
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aop_cmd_db: memory@85f20000 {
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|
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compatible = "qcom,cmd-db";
|
||
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reg = <0x0 0x85f20000 0x0 0x20000>;
|
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|
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no-map;
|
||
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};
|
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|
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sec_apps_mem: sec_apps_region@85fff000 {
|
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|
|
no-map;
|
||
|
|
reg = <0x0 0x85fff000 0x0 0x1000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
smem_region: smem@86000000 {
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x86000000 0x0 0x200000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
removed_region: removed_region@86200000 {
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x86200000 0x0 0x2d00000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pil_camera_mem: camera_region@8ab00000 {
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x8ab00000 0x0 0x500000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pil_modem_mem: modem_region@8b000000 {
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x8b000000 0x0 0x8400000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pil_video_mem: pil_video_region@93400000 {
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x93400000 0x0 0x500000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
wlan_msa_mem: wlan_msa_region@93900000 {
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x93900000 0x0 0x200000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pil_cdsp_mem: cdsp_regions@93b00000 {
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x93b00000 0x0 0x1e00000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pil_adsp_mem: pil_adsp_region@95900000 {
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x95900000 0x0 0x1e00000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pil_ipa_fw_mem: ips_fw_region@97700000 {
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x97700000 0x0 0x10000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pil_ipa_gsi_mem: ipa_gsi_region@97710000 {
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x97710000 0x0 0x5000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pil_gpu_mem: gpu_region@97715000 {
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x97715000 0x0 0x2000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qseecom_mem: qseecom_region {
|
||
|
|
compatible = "shared-dma-pool";
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x9e400000 0x0 0x1400000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cdsp_sec_mem: cdsp_sec_regions@9f800000 {
|
||
|
|
no-map;
|
||
|
|
reg = <0x0 0x9f800000 0x0 0x1e00000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
adsp_mem: adsp_region {
|
||
|
|
compatible = "shared-dma-pool";
|
||
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||
|
|
reusable;
|
||
|
|
alignment = <0x0 0x400000>;
|
||
|
|
size = <0x0 0x800000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sdsp_mem: sdsp_region {
|
||
|
|
compatible = "shared-dma-pool";
|
||
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
||
|
|
reusable;
|
||
|
|
alignment = <0 0x400000>;
|
||
|
|
size = <0 0x400000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
user_contig_mem: user_contig_region {
|
||
|
|
compatible = "shared-dma-pool";
|
||
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||
|
|
reusable;
|
||
|
|
alignment = <0x0 0x400000>;
|
||
|
|
size = <0x0 0x1000000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qseecom_ta_mem: qseecom_ta_region {
|
||
|
|
compatible = "shared-dma-pool";
|
||
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
||
|
|
reusable;
|
||
|
|
alignment = <0 0x400000>;
|
||
|
|
size = <0 0x1000000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
|
||
|
|
compatible = "shared-dma-pool";
|
||
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
|
||
|
|
reusable;
|
||
|
|
alignment = <0 0x400000>;
|
||
|
|
size = <0 0x800000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
secure_display_memory: secure_display_region {
|
||
|
|
compatible = "shared-dma-pool";
|
||
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
||
|
|
reusable;
|
||
|
|
alignment = <0 0x400000>;
|
||
|
|
size = <0 0x8c00000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cont_splash_memory: splash_region {
|
||
|
|
reg = <0x0 0x9c000000 0x0 0x0f00000>;
|
||
|
|
label = "cont_splash_region";
|
||
|
|
};
|
||
|
|
|
||
|
|
dfps_data_memory: dfps_data_region@9cf00000 {
|
||
|
|
reg = <0x0 0x9cf00000 0x0 0x0100000>;
|
||
|
|
label = "dfps_data_region";
|
||
|
|
};
|
||
|
|
|
||
|
|
disp_rdump_memory: disp_rdump_region@9c000000 {
|
||
|
|
reg = <0x0 0x9c000000 0x0 0x01000000>;
|
||
|
|
label = "disp_rdump_region";
|
||
|
|
};
|
||
|
|
|
||
|
|
dump_mem: mem_dump_region {
|
||
|
|
compatible = "shared-dma-pool";
|
||
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
||
|
|
reusable;
|
||
|
|
size = <0 0x2800000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* global autoconfigured region for contiguous allocations */
|
||
|
|
linux,cma {
|
||
|
|
compatible = "shared-dma-pool";
|
||
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
||
|
|
reusable;
|
||
|
|
alignment = <0 0x400000>;
|
||
|
|
size = <0 0x2000000>;
|
||
|
|
linux,cma-default;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
clocks {
|
||
|
|
xo_board: xo_board {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
clock-frequency = <38400000>;
|
||
|
|
clock-output-names = "xo_board";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sleep_clk: sleep_clk {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
clock-frequency = <32000>;
|
||
|
|
clock-output-names = "sleep_clk";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&soc {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0 0 0 0xffffffff>;
|
||
|
|
compatible = "simple-bus";
|
||
|
|
|
||
|
|
apps_rsc: rsc@18200000 {
|
||
|
|
label = "apps_rsc";
|
||
|
|
compatible = "qcom,rpmh-rsc";
|
||
|
|
reg = <0x18200000 0x10000>,
|
||
|
|
<0x18210000 0x10000>,
|
||
|
|
<0x18220000 0x10000>;
|
||
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
||
|
|
qcom,drv-count = <3>;
|
||
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
power-domains = <&CLUSTER_PD>;
|
||
|
|
|
||
|
|
apps_rsc_drv2: drv@2 {
|
||
|
|
qcom,drv-id = <2>;
|
||
|
|
qcom,tcs-offset = <0xd00>;
|
||
|
|
channel@0 {
|
||
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
||
|
|
<SLEEP_TCS 3>,
|
||
|
|
<WAKE_TCS 3>,
|
||
|
|
<CONTROL_TCS 1>,
|
||
|
|
<FAST_PATH_TCS 0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
rpmhcc: clock-controller {
|
||
|
|
compatible = "qcom,sm6150-rpmh-clk";
|
||
|
|
#clock-cells = <1>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
disp_rsc: rsc@af20000 {
|
||
|
|
label = "disp_rsc";
|
||
|
|
compatible = "qcom,rpmh-rsc";
|
||
|
|
reg = <0xaf20000 0x10000>;
|
||
|
|
reg-names = "drv-0";
|
||
|
|
qcom,drv-count = <1>;
|
||
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
|
||
|
|
disp_rsc_drv0: drv@0 {
|
||
|
|
qcom,drv-id = <0>;
|
||
|
|
qcom,tcs-offset = <0x1c00>;
|
||
|
|
channel@0 {
|
||
|
|
qcom,tcs-config = <SLEEP_TCS 1>,
|
||
|
|
<WAKE_TCS 1>,
|
||
|
|
<ACTIVE_TCS 2>,
|
||
|
|
<CONTROL_TCS 0>,
|
||
|
|
<FAST_PATH_TCS 0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
intc: interrupt-controller@17a00000 {
|
||
|
|
compatible = "arm,gic-v3";
|
||
|
|
#interrupt-cells = <3>;
|
||
|
|
interrupt-controller;
|
||
|
|
#redistributor-regions = <1>;
|
||
|
|
redistributor-stride = <0x0 0x20000>;
|
||
|
|
reg = <0x17a00000 0x10000>, /* GICD */
|
||
|
|
<0x17a60000 0x100000>; /* GICR * 8 */
|
||
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-parent = <&intc>;
|
||
|
|
};
|
||
|
|
|
||
|
|
arch_timer: timer {
|
||
|
|
compatible = "arm,armv8-timer";
|
||
|
|
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||
|
|
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||
|
|
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||
|
|
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||
|
|
clock-frequency = <19200000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
timer@17c20000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges;
|
||
|
|
compatible = "arm,armv7-timer-mem";
|
||
|
|
reg = <0x17c20000 0x1000>;
|
||
|
|
clock-frequency = <19200000>;
|
||
|
|
|
||
|
|
frame@17c21000 {
|
||
|
|
frame-number = <0>;
|
||
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0x17c21000 0x1000>,
|
||
|
|
<0x17c22000 0x1000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
frame@17c23000 {
|
||
|
|
frame-number = <1>;
|
||
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0x17c23000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
frame@17c25000 {
|
||
|
|
frame-number = <2>;
|
||
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0x17c25000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
frame@17c27000 {
|
||
|
|
frame-number = <3>;
|
||
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0x17c27000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
frame@17c29000 {
|
||
|
|
frame-number = <4>;
|
||
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0x17c29000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
frame@17c2b000 {
|
||
|
|
frame-number = <5>;
|
||
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0x17c2b000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
frame@17c2d000 {
|
||
|
|
frame-number = <6>;
|
||
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg = <0x17c2d000 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pdc: interrupt-controller@b220000 {
|
||
|
|
compatible = "qcom,sm6150-pdc", "qcom,pdc";
|
||
|
|
reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
|
||
|
|
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
interrupt-parent = <&intc>;
|
||
|
|
interrupt-controller;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-rtb {
|
||
|
|
compatible = "qcom,msm-rtb";
|
||
|
|
qcom,rtb-size = <0x100000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
thermal_zones: thermal-zones {
|
||
|
|
};
|
||
|
|
|
||
|
|
ddr_bwprofiler {
|
||
|
|
compatible = "qcom,ddr_bwprofiler";
|
||
|
|
clocks = <&aoss_qmp QDSS_CLK>;
|
||
|
|
clock-names = "qdss_clk";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_id_1: geniqup@8c0000 {
|
||
|
|
compatible = "qcom,geni-se-qup";
|
||
|
|
reg = <0xac0000 0x6000>;
|
||
|
|
ranges;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
status = "ok";
|
||
|
|
|
||
|
|
uart2: serial@880000 {
|
||
|
|
compatible = "qcom,geni-debug-uart";
|
||
|
|
reg = <0x880000 0x4000>;
|
||
|
|
clock-names = "se";
|
||
|
|
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
status = "ok";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
soc-sleep-stats@c3f0000 {
|
||
|
|
compatible = "qcom,rpmh-sleep-stats-legacy";
|
||
|
|
reg = <0xc3f0000 0x400>;
|
||
|
|
ss-name = "modem", "adsp", "adsp_island",
|
||
|
|
"cdsp", "slpi", "slpi_island",
|
||
|
|
"apss";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
#include "sm6150-pinctrl.dtsi"
|
||
|
|
#include "sm6150-thermal.dtsi"
|