494 lines
16 KiB
Text
494 lines
16 KiB
Text
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&soc {
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/*
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* QUPv3 Instances
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* QUPv3_1 0 : SE 5
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* QUPv3_1 1 : SE 6
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* QUPv3_1 2 : SE 7
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* QUPv3_1 3 : SE 8
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* QUPv3_1 4 : SE 9
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* QUPv3_0 0 : SE 0
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* QUPv3_0 1 : SE 1
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* QUPv3_0 2 : SE 2
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* QUPv3_0 3 : SE 3
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* QUPv3_0 4 : SE 4
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*/
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/* GPI Instance */
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gpi_dma0: qcom,gpi-dma@0x04a00000 {
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#dma-cells = <5>;
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compatible = "qcom,gpi-dma";
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reg = <0x04a00000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ev-factor = <2>;
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qcom,max-num-gpii = <8>;
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qcom,gpii-mask = <0x1f>;
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iommus = <&apps_smmu 0x0136 0x0>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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status = "ok";
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};
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gpi_dma1: qcom,gpi-dma@0x04c00000 {
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#dma-cells = <5>;
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compatible = "qcom,gpi-dma";
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reg = <0x04c00000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ev-factor = <2>;
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qcom,max-num-gpii = <8>;
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qcom,gpii-mask = <0x0f>;
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iommus = <&apps_smmu 0x0156 0x0>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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status = "ok";
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};
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/* QUPv3_0 Instances */
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qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x04ac0000 0x2000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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iommus = <&apps_smmu 0x123 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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ranges;
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status = "ok";
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/* HSUART with 2-wire mode */
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qupv3_se3_2uart: qcom,qup_uart@0x4a8c000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x4a8c000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_2uart_active>;
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pinctrl-1 = <&qupv3_se3_2uart_sleep>;
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interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 3 2 64 0>,
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<&gpi_dma0 1 3 2 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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/* Debug UART Instance for CDP/MTP/RUMI platform */
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qupv3_se4_2uart: qcom,qup_uart@0x4a90000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x4a90000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_2uart_active>;
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pinctrl-1 = <&qupv3_se4_2uart_sleep>;
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interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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qupv3_se0_i2c: i2c@4a80000 {
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compatible = "qcom,i2c-geni";
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reg = <0x04a80000 0x4000>;
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
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<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
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dmas = <&gpi_dma0 0 0 3 64 0>,
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<&gpi_dma0 1 0 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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status = "disabled";
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};
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qupv3_se1_i2c: i2c@4a84000 {
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compatible = "qcom,i2c-geni";
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reg = <0x04a84000 0x4000>;
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interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
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<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
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dmas = <&gpi_dma0 0 1 3 64 0>,
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<&gpi_dma0 1 1 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_i2c_active>;
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pinctrl-1 = <&qupv3_se1_i2c_sleep>;
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status = "disabled";
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};
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qupv3_se2_i2c: i2c@4a88000 {
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compatible = "qcom,i2c-geni";
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reg = <0x04a88000 0x4000>;
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
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<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
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dmas = <&gpi_dma0 0 2 3 64 0>,
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<&gpi_dma0 1 2 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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status = "disabled";
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};
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qupv3_se3_i2c: i2c@4a8c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x04a8c000 0x4000>;
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interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
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<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
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dmas = <&gpi_dma0 0 3 3 64 0>,
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<&gpi_dma0 1 3 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_i2c_active>;
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pinctrl-1 = <&qupv3_se3_i2c_sleep>;
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status = "disabled";
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};
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qupv3_se4_i2c: i2c@4a90000 {
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compatible = "qcom,i2c-geni";
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reg = <0x04a90000 0x4000>;
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interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
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<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
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dmas = <&gpi_dma0 0 4 3 64 0>,
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<&gpi_dma0 1 4 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_i2c_active>;
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pinctrl-1 = <&qupv3_se4_i2c_sleep>;
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status = "disabled";
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};
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/* SPI Instances */
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qupv3_se0_spi: spi@4a80000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x04a80000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_spi_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep>;
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 0 1 64 0>,
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<&gpi_dma0 1 0 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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qupv3_se2_spi: spi@4a88000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x04a88000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
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<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_spi_active>;
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pinctrl-1 = <&qupv3_se2_spi_sleep>;
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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dmas = <&gpi_dma0 0 2 1 64 0>,
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<&gpi_dma0 1 2 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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};
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/* QUPv3_1 instances */
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qupv3_1: qcom,qupv3_1_geni_se@4cc0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x04cc0000 0x2000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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iommus = <&apps_smmu 0x143 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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ranges;
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status = "ok";
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/*
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* HS UART instances. HS UART usecases can be supported on these
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* instances only.
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*/
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qupv3_se9_4uart: qcom,qup_uart@0x4c90000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x4c90000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
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|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
|
||
|
|
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
|
||
|
|
<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
pinctrl-names = "default", "active", "sleep", "shutdown";
|
||
|
|
pinctrl-0 = <&qupv3_se9_default_cts>, <&qupv3_se9_default_rx>, <&qupv3_se9_default_rts>,
|
||
|
|
<&qupv3_se9_default_tx>;
|
||
|
|
pinctrl-1 = <&qupv3_se9_cts>, <&qupv3_se9_rx>, <&qupv3_se9_rts>,
|
||
|
|
<&qupv3_se9_tx>;
|
||
|
|
pinctrl-2 = <&qupv3_se9_cts>, <&qupv3_se9_default_rx>, <&qupv3_se9_rts>,
|
||
|
|
<&qupv3_se9_tx>;
|
||
|
|
pinctrl-3 = <&qupv3_se9_default_cts>, <&qupv3_se9_default_rx>, <&qupv3_se9_default_rts>,
|
||
|
|
<&qupv3_se9_default_tx>;
|
||
|
|
interrupts-extended = <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&tlmm 13 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
qcom,wakeup-byte = <0xFD>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* I2C */
|
||
|
|
qupv3_se5_i2c: i2c@4c80000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0x04c80000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
|
||
|
|
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
|
||
|
|
<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
dmas = <&gpi_dma1 0 0 3 64 0>,
|
||
|
|
<&gpi_dma1 1 0 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se5_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se6_i2c: i2c@4c84000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0x04c84000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
|
||
|
|
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
|
||
|
|
<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
dmas = <&gpi_dma1 0 1 3 64 0>,
|
||
|
|
<&gpi_dma1 1 1 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se6_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se7_i2c: i2c@4c88000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0x04c88000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
|
||
|
|
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
|
||
|
|
<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
dmas = <&gpi_dma1 0 2 3 64 0>,
|
||
|
|
<&gpi_dma1 1 2 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se7_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se7_i2c_sleep>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se8_i2c: i2c@4c8c000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0x04c8c000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
|
||
|
|
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
|
||
|
|
<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
dmas = <&gpi_dma1 0 3 3 64 0>,
|
||
|
|
<&gpi_dma1 1 3 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se8_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se9_i2c: i2c@4c90000 {
|
||
|
|
compatible = "qcom,i2c-geni";
|
||
|
|
reg = <0x04c90000 0x4000>;
|
||
|
|
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
|
||
|
|
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
|
||
|
|
<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
dmas = <&gpi_dma1 0 4 3 64 0>,
|
||
|
|
<&gpi_dma1 1 4 3 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se9_i2c_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se6_spi: spi@4c84000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0x04c84000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
|
||
|
|
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
|
||
|
|
<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se6_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se6_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
dmas = <&gpi_dma1 0 1 1 64 0>,
|
||
|
|
<&gpi_dma1 1 1 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se8_spi: spi@4c8c000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0x04c8c000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||
|
|
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||
|
|
interconnects =
|
||
|
|
<&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
|
||
|
|
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_1>,
|
||
|
|
<&system_noc MASTER_QUP_1 &bimc SLAVE_EBI_CH0>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se8_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se8_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&gpi_dma1 0 3 1 64 0>,
|
||
|
|
<&gpi_dma1 1 3 1 64 0>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_se9_spi: spi@4c90000 {
|
||
|
|
compatible = "qcom,spi-geni";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg = <0x04c90000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk";
|
||
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se9_spi_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se9_spi_sleep>;
|
||
|
|
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
dmas = <&gpi_dma1 0 4 1 64 0>,
|
||
|
|
<&gpi_dma1 1 4 1 64 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|