254 lines
5.2 KiB
Text
254 lines
5.2 KiB
Text
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#include <dt-bindings/interconnect/qcom,waipio.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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&mdm0 {
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compatible = "qcom,ext-lemur";
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qcom,mdm-link-info = "0308_01.01.00";
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};
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&modem_pas {
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status = "disabled";
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};
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&pcie1 {
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qcom,target-link-width = <1>; /* force X1 lane width */
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qcom,panic-genspeed-mismatch;
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qcom,no-l0s-supported;
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qcom,target-link-speed = <4>; /* Set max link speed to Gen4 */
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qcom,vreg-0p9-voltage-level = <912000 912000 193000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000
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/* Gen4 */
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RPMH_REGULATOR_LEVEL_NOM
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RPMH_REGULATOR_LEVEL_NOM
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100000000>;
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qcom,pcie-phy-ver = <105>;
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qcom,phy-sequence = <0x1240 0x03 0x0
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0x101c 0x31 0x0
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0x1020 0x01 0x0
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0x1024 0xde 0x0
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0x1028 0x07 0x0
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0x1030 0x97 0x0
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0x1034 0x0c 0x0
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0x1044 0x14 0x0
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0x1048 0x90 0x0
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0x1058 0x0f 0x0
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0x1074 0x06 0x0
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0x1078 0x06 0x0
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0x107c 0x16 0x0
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0x1080 0x16 0x0
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0x1084 0x36 0x0
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0x1088 0x36 0x0
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0x1094 0x08 0x0
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0x10a4 0x46 0x0
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0x10a8 0x04 0x0
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0x10ac 0x0a 0x0
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0x10b0 0x1a 0x0
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0x10b4 0x14 0x0
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0x10b8 0x34 0x0
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0x10bc 0x82 0x0
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0x10c4 0xd0 0x0
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0x10cc 0x55 0x0
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0x10d0 0x55 0x0
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0x10d4 0x03 0x0
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0x10d8 0x55 0x0
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0x10dc 0x55 0x0
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0x10e0 0x05 0x0
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0x110c 0x02 0x0
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0x1154 0x34 0x0
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0x1158 0x12 0x0
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0x115c 0x00 0x0
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0x1168 0x0a 0x0
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0x116c 0x04 0x0
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0x119c 0x88 0x0
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0x1174 0x20 0x0
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0x117c 0x06 0x0
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0x11a0 0x14 0x0
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0x11a8 0x0f 0x0
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0x0220 0x16 0x0
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0x03c0 0x38 0x0
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0x0a20 0x16 0x0
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0x0bc0 0x38 0x0
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0x0364 0xcc 0x0
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0x0368 0x12 0x0
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0x036c 0xcc 0x0
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0x0374 0x4a 0x0
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0x0378 0x29 0x0
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0x037c 0xc5 0x0
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0x0380 0xad 0x0
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0x0384 0xb6 0x0
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0x0388 0xc0 0x0
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0x038c 0x1f 0x0
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0x0390 0xfb 0x0
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0x0394 0x0f 0x0
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0x0398 0xc7 0x0
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0x039c 0xef 0x0
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0x03a0 0xbf 0x0
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0x03a4 0xa0 0x0
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0x03a8 0x81 0x0
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0x03ac 0xde 0x0
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0x03b0 0x7f 0x0
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0x0b64 0xcc 0x0
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0x0b68 0x12 0x0
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0x0b6c 0xcc 0x0
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0x0b74 0x4a 0x0
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0x0b78 0x29 0x0
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0x0b7c 0xc5 0x0
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0x0b80 0xad 0x0
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0x0b84 0xb6 0x0
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0x0b88 0xc0 0x0
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0x0b8c 0x1f 0x0
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0x0b90 0xfb 0x0
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0x0b94 0x0f 0x0
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0x0b98 0xc7 0x0
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0x0b9c 0xef 0x0
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0x0ba0 0xbf 0x0
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0x0ba4 0xa0 0x0
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0x0ba8 0x81 0x0
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0x0bac 0xde 0x0
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0x0bb0 0x7f 0x0
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0x03b4 0x20 0x0
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0x022c 0x3f 0x0
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0x0230 0x37 0x0
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0x0bb4 0x20 0x0
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0x0a2c 0x3f 0x0
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0x0a30 0x37 0x0
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0x0078 0x05 0x0
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0x007c 0xf6 0x0
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0x0878 0x05 0x0
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0x087c 0xf6 0x0
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0x0290 0x05 0x0
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0x0a90 0x05 0x0
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0x03f8 0x1f 0x0
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0x0400 0x1f 0x0
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0x0408 0x1f 0x0
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0x0410 0x1f 0x0
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0x0418 0x1f 0x0
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0x0420 0x1f 0x0
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0x03f4 0x1f 0x0
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0x03fc 0x1f 0x0
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0x0404 0x1f 0x0
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0x0bf8 0x1f 0x0
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0x0c00 0x1f 0x0
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0x0c08 0x1f 0x0
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0x0c10 0x1f 0x0
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0x0c18 0x1f 0x0
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0x0c20 0x1f 0x0
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0x0bf4 0x1f 0x0
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0x0bfc 0x1f 0x0
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0x0c04 0x1f 0x0
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0x0208 0x0c 0x0
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0x0a08 0x0c 0x0
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0x020c 0x0a 0x0
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0x0a0c 0x0a 0x0
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0x02dc 0x0a 0x0
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0x0adc 0x0a 0x0
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0x0308 0x0b 0x0
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0x0b08 0x0b 0x0
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0x027c 0x10 0x0
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0x0a7c 0x10 0x0
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0x02b4 0x00 0x0
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0x0ab4 0x00 0x0
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0x02ec 0x0f 0x0
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0x0aec 0x0f 0x0
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0x02c4 0x00 0x0
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0x02c8 0x1f 0x0
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0x0ac4 0x00 0x0
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0x0ac8 0x1f 0x0
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0x0030 0x1a 0x0
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0x0034 0x0c 0x0
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0x0830 0x1a 0x0
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0x0834 0x0c 0x0
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0x141c 0xc1 0x0
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0x1490 0x00 0x0
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0x13e0 0x16 0x0
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0x13e4 0x22 0x0
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0x1508 0x02 0x0
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0x14a0 0x16 0x0
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0x1584 0x28 0x0
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0x1370 0x2e 0x0
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0x155c 0x2e 0x0
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0x1388 0x99 0x0
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0x1e24 0x01 0x0
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0x1e28 0x01 0x0
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0x1828 0x50 0x0
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0x1c28 0x50 0x0
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0x1200 0x00 0x0
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0x1244 0x03 0x0>;
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};
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&soc {
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qcom,ipa-mpm {
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compatible = "qcom,ipa-mpm";
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qcom,iova-mapping = <0x10000000 0x0FFFFFFF>;
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};
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qcom,qbt_handler {
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status = "disabled";
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};
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};
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&ipa_hw {
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status = "ok";
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qcom,platform-type = <2>; /* APQ platform */
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qcom,entire-ipa-block-size = <0x100000>;
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qcom,register-collection-on-crash;
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qcom,testbus-collection-on-crash;
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qcom,non-tn-collection-on-crash;
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qcom,ram-collection-on-crash;
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qcom,secure-debug-check-action = <0>;
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};
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&tlmm {
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qcom,gpios-reserved = <28 29 30 31>;
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};
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&pcie1_rp {
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#address-cells = <5>;
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#size-cells = <0>;
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mhi0: qcom,mhi@0 {
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reg = <0 0 0 0 0 >;
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esoc-names = "mdm";
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esoc-0 = <&mdm0>;
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interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
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interconnect-names = "pcie_to_ddr";
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qcom,mhi-bus-bw-cfg =
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<0 0>, /* no vote */
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<250000 0>, /* avg bw / AB: 2 GBps, peak bw / IB: no vote */
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<500000 0>, /* avg bw / AB: 4 GBps, peak bw / IB: no vote */
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<1000000 0>, /* avg bw / AB: 8 GBps, peak bw / IB: no vote */
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<2000000 0>; /* avg bw / AB: 16 GBps, peak bw / IB: no vote */
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qcom,iommu-group = <&mhi0_iommu_group>;
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#address-cells = <1>;
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#size-cells = <1>;
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mhi0_iommu_group: mhi0_iommu_group {
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qcom,iommu-msi-size = <0x1000>;
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qcom,iommu-dma-addr-pool = <0x20000000 0x0fffffff>;
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qcom,iommu-dma = "fastmap";
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qcom,iommu-pagetable = "coherent";
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};
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};
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};
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