341 lines
8.5 KiB
C
341 lines
8.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,videocc-trinket.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "common.h"
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#include "reset.h"
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#include "vdd-level.h"
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static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
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static struct clk_vdd_class *video_cc_trinket_regulators[] = {
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&vdd_cx,
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};
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enum {
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P_BI_TCXO,
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P_SLEEP_CLK,
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P_VIDEO_PLL0_OUT_AUX,
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P_VIDEO_PLL0_OUT_AUX2,
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P_VIDEO_PLL0_OUT_MAIN,
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};
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static const struct pll_vco spark_vco[] = {
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{ 1000000000, 2000000000, 0 },
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{ 750000000, 1500000000, 1 },
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{ 500000000, 1000000000, 2 },
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{ 300000000, 500000000, 3 },
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{ 550000000, 1100000000, 4 },
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};
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/* 600MHz configuration */
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static const struct alpha_pll_config video_pll0_config = {
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.l = 0x1F,
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.alpha_hi = 0x40,
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.alpha = 0x00,
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.alpha_en_mask = BIT(24),
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.vco_val = 0x2 << 20,
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.vco_mask = 0x3 << 20,
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.main_output_mask = BIT(0),
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.config_ctl_val = 0x4001055b,
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};
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static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
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[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_ALPHA_VAL_U] = 0x0c,
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[PLL_OFF_USER_CTL] = 0x10,
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[PLL_OFF_USER_CTL_U] = 0x14,
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[PLL_OFF_CONFIG_CTL] = 0x18,
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[PLL_OFF_TEST_CTL] = 0x1C,
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[PLL_OFF_TEST_CTL_U] = 0x20,
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},
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};
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static struct clk_alpha_pll video_pll0 = {
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.offset = 0x42c,
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.vco_table = spark_vco,
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.num_vco = ARRAY_SIZE(spark_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.clkr = {
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.hw.init = &(const struct clk_init_data){
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.name = "video_pll0",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 1100000000,
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[VDD_NOMINAL] = 2000000000},
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},
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},
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};
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static const struct parent_map video_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_VIDEO_PLL0_OUT_MAIN, 1 },
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{ P_VIDEO_PLL0_OUT_AUX, 2 },
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{ P_VIDEO_PLL0_OUT_AUX2, 3 },
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};
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static const struct clk_parent_data video_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &video_pll0.clkr.hw },
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{ .hw = &video_pll0.clkr.hw },
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{ .hw = &video_pll0.clkr.hw },
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};
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static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(133333333, P_VIDEO_PLL0_OUT_MAIN, 4.5, 0, 0),
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F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0),
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F(300000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(380000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(410000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(460000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_venus_clk_src = {
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.cmd_rcgr = 0x7f0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_0,
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.freq_tbl = ftbl_video_cc_venus_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "video_cc_venus_clk_src",
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.parent_data = video_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 133333333,
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[VDD_LOW] = 240000000,
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[VDD_LOW_L1] = 300000000,
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[VDD_NOMINAL] = 380000000,
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[VDD_NOMINAL_L1] = 410000000,
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[VDD_HIGH] = 460000000},
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},
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};
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static struct clk_branch video_cc_apb_clk = {
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.halt_reg = 0x990,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x990,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "video_cc_apb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_vcodec0_axi_clk = {
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.halt_reg = 0x8f0,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x8f0,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "video_cc_vcodec0_axi_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_vcodec0_core_clk = {
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.halt_reg = 0x890,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x890,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "video_cc_vcodec0_core_clk",
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.parent_hws = (const struct clk_hw*[]){
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&video_cc_venus_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_venus_ahb_clk = {
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.halt_reg = 0x9b0,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x9b0,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "video_cc_venus_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_venus_ctl_axi_clk = {
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.halt_reg = 0x8d0,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x8d0,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "video_cc_venus_ctl_axi_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_venus_ctl_core_clk = {
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.halt_reg = 0x850,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x850,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "video_cc_venus_ctl_core_clk",
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.parent_hws = (const struct clk_hw*[]){
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&video_cc_venus_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_regmap *video_cc_trinket_clocks[] = {
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[VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr,
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[VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
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[VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
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[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
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[VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
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[VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
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[VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
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[VIDEO_CC_PLL0] = &video_pll0.clkr,
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};
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static const struct qcom_reset_map video_cc_trinket_resets[] = {
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[VIDEO_CC_INTERFACE_BCR] = { 0x8b0 },
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[VIDEO_CC_VCODEC0_BCR] = { 0x870 },
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[VIDEO_CC_VENUS_BCR] = { 0x810 },
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};
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static const struct regmap_config video_cc_trinket_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0xb94,
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.fast_io = true,
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};
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static const struct qcom_cc_desc video_cc_trinket_desc = {
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.config = &video_cc_trinket_regmap_config,
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.clks = video_cc_trinket_clocks,
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.num_clks = ARRAY_SIZE(video_cc_trinket_clocks),
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.resets = video_cc_trinket_resets,
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.num_resets = ARRAY_SIZE(video_cc_trinket_resets),
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.clk_regulators = video_cc_trinket_regulators,
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.num_clk_regulators = ARRAY_SIZE(video_cc_trinket_regulators),
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};
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static const struct of_device_id video_cc_trinket_match_table[] = {
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{ .compatible = "qcom,trinket-videocc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, video_cc_trinket_match_table);
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static int video_cc_trinket_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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int ret;
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regmap = qcom_cc_map(pdev, &video_cc_trinket_desc);
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if (IS_ERR(regmap)) {
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pr_err("Failed to map the video_cc registers\n");
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return PTR_ERR(regmap);
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}
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clk_alpha_pll_configure(&video_pll0, regmap, &video_pll0_config);
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/*
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* Keep clocks always enabled:
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* video_cc_sleep_clk
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* video_cc_xo_clk
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*/
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regmap_update_bits(regmap, 0xb18, BIT(0), BIT(0));
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regmap_update_bits(regmap, 0xab8, BIT(0), BIT(0));
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ret = qcom_cc_really_probe(pdev, &video_cc_trinket_desc, regmap);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register VIDEO CC clocks\n");
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return ret;
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}
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dev_info(&pdev->dev, "Registered VIDEO CC clocks\n");
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return ret;
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}
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static void video_cc_trinket_sync_state(struct device *dev)
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{
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qcom_cc_sync_state(dev, &video_cc_trinket_desc);
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}
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static struct platform_driver video_cc_trinket_driver = {
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.probe = video_cc_trinket_probe,
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.driver = {
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.name = "video_cc-trinket",
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.of_match_table = video_cc_trinket_match_table,
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.sync_state = video_cc_trinket_sync_state,
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},
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};
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static int __init video_cc_trinket_init(void)
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{
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return platform_driver_register(&video_cc_trinket_driver);
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}
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subsys_initcall(video_cc_trinket_init);
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static void __exit video_cc_trinket_exit(void)
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{
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platform_driver_unregister(&video_cc_trinket_driver);
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}
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module_exit(video_cc_trinket_exit);
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MODULE_DESCRIPTION("QTI VIDEO_CC TRINKET Driver");
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MODULE_LICENSE("GPL v2");
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