139 lines
4.1 KiB
C
139 lines
4.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __QG_REG_H__
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#define __QG_REG_H__
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#define PERPH_TYPE_REG 0x04
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#define PERPH_SUBTYPE_REG 0x05
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#define QG_ADC_IBAT_5A 0x3
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#define QG_ADC_IBAT_10A 0x4
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#define QG_TYPE 0x0D
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#define QG_STATUS1_REG 0x08
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#define QG_OK_BIT BIT(7)
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#define BATTERY_PRESENT_BIT BIT(0)
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#define ESR_MEAS_DONE_BIT BIT(4)
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#define QG_STATUS2_REG 0x09
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#define BATTERY_MISSING_BIT BIT(3)
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#define GOOD_OCV_BIT BIT(1)
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#define QG_STATUS3_REG 0x0A
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#define COUNT_FIFO_RT_MASK GENMASK(3, 0)
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#define QG_STATUS4_REG 0x0B
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#define ESR_MEAS_IN_PROGRESS_BIT BIT(4)
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#define QG_INT_RT_STS_REG 0x10
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#define FIFO_UPDATE_DONE_RT_STS_BIT BIT(3)
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#define VBAT_LOW_INT_RT_STS_BIT BIT(1)
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#define BATTERY_MISSING_INT_RT_STS_BIT BIT(0)
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#define QG_INT_LATCHED_STS_REG 0x18
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#define FIFO_UPDATE_DONE_INT_LAT_STS_BIT BIT(3)
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#define QG_STATE_TRIG_CMD_REG 0x40
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#define S7_PON_OCV_START BIT(3)
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#define QG_DATA_CTL1_REG 0x41
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#define MASTER_HOLD_OR_CLR_BIT BIT(0)
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#define QG_DATA_CTL2_REG 0x42
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#define BURST_AVG_HOLD_FOR_READ_BIT BIT(0)
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#define QG_MODE_CTL1_REG 0x43
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#define PARALLEL_IBAT_SENSE_EN_BIT BIT(7)
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#define QG_MODE_CTL2_REG 0x44
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#define VI_MODE_BIT BIT(0)
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#define QG_VBAT_EMPTY_THRESHOLD_REG 0x4B
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#define QG_VBAT_LOW_THRESHOLD_REG 0x4C
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#define QG_S2_NORMAL_MEAS_CTL2_REG 0x51
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#define FIFO_LENGTH_MASK GENMASK(5, 3)
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#define FIFO_LENGTH_SHIFT 3
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#define NUM_OF_ACCUM_MASK GENMASK(2, 0)
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#define QG_S2_NORMAL_MEAS_CTL3_REG 0x52
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#define QG_S3_SLEEP_OCV_MEAS_CTL4_REG 0x59
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#define S3_SLEEP_OCV_TIMER_MASK GENMASK(2, 0)
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#define QG_S3_SLEEP_OCV_TREND_CTL2_REG 0x5C
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#define TREND_TOL_MASK GENMASK(5, 0)
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#define QG_S3_SLEEP_OCV_IBAT_CTL1_REG 0x5D
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#define SLEEP_IBAT_QUALIFIED_LENGTH_MASK GENMASK(2, 0)
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#define QG_S3_ENTRY_IBAT_THRESHOLD_REG 0x5E
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#define QG_S3_EXIT_IBAT_THRESHOLD_REG 0x5F
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#define QG_S5_OCV_VALIDATE_MEAS_CTL1_REG 0x60
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#define ALLOW_S5_BIT BIT(7)
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#define QG_S7_PON_OCV_MEAS_CTL1_REG 0x64
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#define ADC_CONV_DLY_MASK GENMASK(3, 0)
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#define QG_ESR_MEAS_TRIG_REG 0x68
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#define HW_ESR_MEAS_START_BIT BIT(0)
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#define QG_S7_PON_OCV_V_DATA0_REG 0x70
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#define QG_S7_PON_OCV_I_DATA0_REG 0x72
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#define QG_S3_GOOD_OCV_V_DATA0_REG 0x74
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#define QG_S3_GOOD_OCV_I_DATA0_REG 0x76
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#define QG_PRE_ESR_V_DATA0_REG 0x78
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#define QG_PRE_ESR_I_DATA0_REG 0x7A
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#define QG_POST_ESR_V_DATA0_REG 0x7C
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#define QG_POST_ESR_I_DATA0_REG 0x7E
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#define QG_S2_NORMAL_AVG_V_DATA0_REG 0x80
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#define QG_S2_NORMAL_AVG_I_DATA0_REG 0x82
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#define QG_V_ACCUM_DATA0_RT_REG 0x88
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#define QG_I_ACCUM_DATA0_RT_REG 0x8B
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#define QG_ACCUM_CNT_RT_REG 0x8E
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#define QG_V_FIFO0_DATA0_REG 0x90
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#define QG_I_FIFO0_DATA0_REG 0xA0
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#define QG_SOC_MONOTONIC_REG 0xBF
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#define QG_LAST_ADC_V_DATA0_REG 0xC0
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#define QG_LAST_ADC_I_DATA0_REG 0xC2
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#define QG_LAST_BURST_AVG_I_DATA0_REG 0xC6
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#define QG_LAST_S3_SLEEP_V_DATA0_REG 0xCC
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/* SDAM offsets */
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#define QG_SDAM_VALID_OFFSET 0x46 /* 1-byte 0x46 */
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#define QG_SDAM_SOC_OFFSET 0x47 /* 1-byte 0x47 */
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#define QG_SDAM_TEMP_OFFSET 0x48 /* 2-byte 0x48-0x49 */
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#define QG_SDAM_RBAT_OFFSET 0x4A /* 2-byte 0x4A-0x4B */
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#define QG_SDAM_OCV_OFFSET 0x4C /* 4-byte 0x4C-0x4F */
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#define QG_SDAM_IBAT_OFFSET 0x50 /* 4-byte 0x50-0x53 */
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#define QG_SDAM_TIME_OFFSET 0x54 /* 4-byte 0x54-0x57 */
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#define QG_SDAM_CYCLE_COUNT_OFFSET 0x58 /* 16-byte 0x58-0x67 */
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#define QG_SDAM_LEARNED_CAPACITY_OFFSET 0x68 /* 2-byte 0x68-0x69 */
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#define QG_SDAM_ESR_CHARGE_DELTA_OFFSET 0x6A /* 4-byte 0x6A-0x6D */
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#define QG_SDAM_ESR_DISCHARGE_DELTA_OFFSET 0x6E /* 4-byte 0x6E-0x71 */
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#define QG_SDAM_ESR_CHARGE_SF_OFFSET 0x72 /* 2-byte 0x72-0x73 */
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#define QG_SDAM_ESR_DISCHARGE_SF_OFFSET 0x74 /* 2-byte 0x74-0x75 */
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#define QG_SDAM_BATT_AGE_LEVEL_OFFSET 0x76 /* 1-byte 0x76 */
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#define QG_SDAM_MAGIC_OFFSET 0x80 /* 4-byte 0x80-0x83 */
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#define QG_SDAM_FLASH_OCV_OFFSET 0x84 /* 1-byte 0x84 */
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#define QG_SDAM_MAX_OFFSET 0xA4
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/* Below offset is used by PBS */
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#define QG_SDAM_PON_OCV_OFFSET 0xBC /* 2-byte 0xBC-0xBD */
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#endif
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