363 lines
13 KiB
C
363 lines
13 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _SOC_QCOM_LLCC_PERFMON_H_
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#define _SOC_QCOM_LLCC_PERFMON_H_
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#define LLCC_VER4 (41)
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#define LLCC_VER2 (21)
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#define VER_CHK(v) (v >= LLCC_VER2) //check LLCC version 2
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#define VER_CHK4(v) (v >= LLCC_VER4) //check LLCC version 4
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/* COMMON */
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#define LLCC_COMMON_HW_INFO(v) (VER_CHK(v) ? 0x34000 : 0x30000)
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#define LLCC_COMMON_STATUS0(v) (VER_CHK(v) ? 0x3400C : 0x3000C)
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/* FEAC */
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#define FEAC_PROF_FILTER_0_CFG1(v) (VER_CHK(v) ? 0x43004 : 0x037004)
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#define FEAC_PROF_FILTER_0_CFG2(v) (VER_CHK(v) ? 0x43008 : 0x037008)
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#define FEAC_PROF_FILTER_0_CFG3(v) (VER_CHK(v) ? 0x4300C : 0x03700C)
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#define FEAC_PROF_FILTER_0_CFG5(v) (VER_CHK(v) ? 0x43014 : 0x037014)
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#define FEAC_PROF_FILTER_0_CFG6(v) (VER_CHK(v) ? 0x43018 : 0x037018)
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#define FEAC_PROF_FILTER_0_CFG7(v) (VER_CHK(v) ? 0x4301C : 0x03701C)
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#define FEAC_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x43060 : 0x037060) \
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+ 4 * (n))
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#define FEAC_PROF_CFG(v) (VER_CHK(v) ? 0x430A0 : 0x0370A0)
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/* FERC */
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#define FERC_PROF_FILTER_0_CFG0(v) (VER_CHK(v) ? 0x49000 : 0x03B000)
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#define FERC_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x49020 : 0x03B020) \
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+ 4 * (n))
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#define FERC_PROF_CFG(v) (VER_CHK(v) ? 0x49060 : 0x03B060)
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/* FEWC */
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#define FEWC_PROF_FILTER_0_CFG0(v) (VER_CHK(v) ? 0x39000 : 0x033000)
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#define FEWC_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x39020 : 0x033020) \
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+ 4 * (n))
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/* BEAC */
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#define BEAC0_PROF_FILTER_0_CFG3(v) (VER_CHK(v) ? 0x6100C : 0x04900C)
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#define BEAC0_PROF_FILTER_0_CFG4(v) (VER_CHK(v) ? 0x61010 : 0x049010)
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#define BEAC0_PROF_FILTER_0_CFG5(v) (VER_CHK(v) ? 0x61014 : 0x049014)
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#define BEAC0_PROF_FILTER_0_CFG2(v) (VER_CHK(v) ? 0x61008 : 0x049008)
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#define BEAC0_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x61040 : 0x049040) \
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+ 4 * (n))
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#define BEAC0_PROF_CFG(v) (VER_CHK(v) ? 0x61080 : 0x049080)
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#define BEAC_INST_OFF (0x4000)
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/* BERC */
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#define BERC_PROF_FILTER_0_CFG0(v) (VER_CHK(v) ? 0x3D000 : 0x039000)
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#define BERC_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x3D020 : 0x039020) \
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+ 4 * (n))
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#define BERC_PROF_CFG(v) (VER_CHK(v) ? 0x3D060 : 0x039060)
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/* TRP */
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#define TRP_PROF_FILTER_0_CFG1 (0x024004)
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#define TRP_PROF_FILTER_0_CFG2 (0x024008)
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#define TRP_PROF_EVENT_n_CFG(n) (0x024020 + 4 * (n))
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#define TRP_SCID_n_STATUS(n) (0x000004 + 0x1000 * (n))
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/* DRP */
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#define DRP_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x51010 : 0x044010) \
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+ 4 * (n))
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#define DRP_PROF_CFG(v) (VER_CHK(v) ? 0x51050 : 0x044050)
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/* PMGR */
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#define PMGR_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x4D000 : 0x03F000) \
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+ 4 * (n))
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#define PERFMON_COUNTER_n_CONFIG(v, n) ((VER_CHK(v) ? 0x36020 : 0x031020) \
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+ 4 * (n))
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#define PERFMON_MODE(v) (VER_CHK(v) ? 0x3600C : 0x03100C)
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#define PERFMON_DUMP(v) (VER_CHK4(v) ? 0x37000 : VER_CHK(v) ? \
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0x36010 : 0x031010)
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#define LLCC_COUNTER_n_VALUE(v, n) ((VER_CHK4(v) ? 0x37008 : VER_CHK(v) ?\
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0x36060 : 0x31060) + 4 * (n))
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#define EVENT_NUM_MAX (256)
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#define SCID_MAX (32)
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/* Perfmon */
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#define CLEAR_ON_ENABLE BIT(31)
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#define CLEAR_ON_DUMP BIT(30)
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#define FREEZE_ON_SATURATE BIT(29)
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#define CHAINING_EN BIT(28)
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#define COUNT_CLOCK_EVENT BIT(24)
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#define EVENT_SELECT_SHIFT (16)
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#define PERFMON_EVENT_SELECT_MASK GENMASK(EVENT_SELECT_SHIFT + 4,\
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EVENT_SELECT_SHIFT)
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#define PORT_SELECT_SHIFT (0)
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#define PERFMON_PORT_SELECT_MASK GENMASK(PORT_SELECT_SHIFT + 3,\
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PORT_SELECT_SHIFT)
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#define MANUAL_MODE (0)
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#define TIMED_MODE (1)
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#define TRIGGER_MODE (2)
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#define MONITOR_EN_SHIFT (15)
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#define MONITOR_EN BIT(MONITOR_EN_SHIFT)
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#define PERFMON_MODE_MONITOR_EN_MASK GENMASK(MONITOR_EN_SHIFT + 0,\
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MONITOR_EN_SHIFT)
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#define MONITOR_MODE_SHIFT (0)
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#define PERFMON_MODE_MONITOR_MODE_MASK GENMASK(MONITOR_MODE_SHIFT + 0,\
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MONITOR_MODE_SHIFT)
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#define MONITOR_DUMP BIT(0)
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/* COMMON */
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#define BYTE_SCALING (1024)
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#define BEAT_SCALING (32)
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#define LB_CNT_SHIFT (28)
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#define LB_CNT_MASK GENMASK(LB_CNT_SHIFT + 3, \
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LB_CNT_SHIFT)
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#define NUM_MC_SHIFT (10)
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#define NUM_MC_MASK GENMASK(NUM_MC_SHIFT + 1, \
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NUM_MC_SHIFT)
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#define BYTE_SCALING_SHIFT (16)
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#define PROF_CFG_BYTE_SCALING_MASK GENMASK(BYTE_SCALING_SHIFT + 11,\
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BYTE_SCALING_SHIFT)
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#define BEAT_SCALING_SHIFT (8)
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#define PROF_CFG_BEAT_SCALING_MASK GENMASK(BEAT_SCALING_SHIFT + 7,\
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BEAT_SCALING_SHIFT)
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#define PROF_EN_SHIFT (0)
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#define PROF_EN BIT(PROF_EN_SHIFT)
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#define PROF_CFG_EN_MASK GENMASK(PROF_EN_SHIFT + 0,\
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PROF_EN_SHIFT)
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#define FILTER_EN_SHIFT (31)
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#define FILTER_EN BIT(FILTER_EN_SHIFT)
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#define FILTER_EN_MASK GENMASK(FILTER_EN_SHIFT + 0,\
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FILTER_EN_SHIFT)
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#define FILTER_0 (0)
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#define FILTER_0_MASK GENMASK(FILTER_0 + 0, \
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FILTER_0)
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#define FILTER_1 (1)
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#define FILTER_1_MASK GENMASK(FILTER_1 + 0, \
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FILTER_1)
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#define FILTER_SEL_SHIFT (16)
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#define FILTER_SEL_MASK GENMASK(FILTER_SEL_SHIFT + 0,\
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FILTER_SEL_SHIFT)
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#define EVENT_SEL_SHIFT (0)
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#define EVENT_SEL_MASK GENMASK(EVENT_SEL_SHIFT + 5,\
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EVENT_SEL_SHIFT)
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#define EVENT_SEL_MASK7 GENMASK(EVENT_SEL_SHIFT + 6,\
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EVENT_SEL_SHIFT)
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#define EVENT_SEL_MASK8 GENMASK(EVENT_SEL_SHIFT + 7,\
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EVENT_SEL_SHIFT)
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#define MEMTAGOPS_MASK_SHIFT (12)
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#define MEMTAGOPS_MASK_MASK GENMASK(MEMTAGOPS_MASK_SHIFT + 2, \
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MEMTAGOPS_MASK_SHIFT)
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#define MEMTAGOPS_MATCH_SHIFT (10)
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#define MEMTAGOPS_MATCH_MASK GENMASK(MEMTAGOPS_MATCH_SHIFT + 2, \
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MEMTAGOPS_MATCH_SHIFT)
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#define DIRTYINFO_MASK_SHIFT (1)
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#define DIRTYINFO_MASK_MASK GENMASK(DIRTYINFO_MASK_SHIFT + 1, \
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DIRTYINFO_MASK_SHIFT)
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#define DIRTYINFO_MATCH_SHIFT (0)
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#define DIRTYINFO_MATCH_MASK GENMASK(DIRTYINFO_MATCH_SHIFT + 1, \
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DIRTYINFO_MATCH_SHIFT)
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#define CACHEALLOC_MASK_SHIFT (16)
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#define CACHEALLOC_MASK_MASK GENMASK(CACHEALLOC_MASK_SHIFT + 3, \
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CACHEALLOC_MASK_SHIFT)
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#define CACHEALLOC_MATCH_SHIFT (12)
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#define CACHEALLOC_MATCH_MASK GENMASK(CACHEALLOC_MATCH_SHIFT + 3, \
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CACHEALLOC_MATCH_SHIFT)
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#define OPCODE_MASK_SHIFT (28)
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#define OPCODE_MASK_MASK GENMASK(OPCODE_MASK_SHIFT + 3, \
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OPCODE_MASK_SHIFT)
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#define OPCODE_MATCH_SHIFT (24)
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#define OPCODE_MATCH_MASK GENMASK(OPCODE_MATCH_SHIFT + 3, \
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OPCODE_MATCH_SHIFT)
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#define MID_MASK_SHIFT (16)
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#define MID_MASK_MASK GENMASK(MID_MASK_SHIFT + 15, \
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MID_MASK_SHIFT)
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#define MID_MATCH_SHIFT (0)
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#define MID_MATCH_MASK GENMASK(MID_MATCH_SHIFT + 15, \
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MID_MATCH_SHIFT)
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#define SCID_MASK_SHIFT (16)
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#define SCID_MASK_MASK GENMASK(SCID_MASK_SHIFT + 15, \
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SCID_MASK_SHIFT)
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#define SCID_MATCH_SHIFT (0)
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#define SCID_MATCH_MASK GENMASK(SCID_MATCH_SHIFT + 15, \
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SCID_MATCH_SHIFT)
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#define SCID_MULTI_MATCH_SHIFT (0)
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#define SCID_MULTI_MATCH_MASK GENMASK(SCID_MULTI_MATCH_SHIFT + 31, \
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SCID_MULTI_MATCH_SHIFT)
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#define PROFTAG_MASK_SHIFT (2)
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#define PROFTAG_MASK_MASK GENMASK(PROFTAG_MASK_SHIFT + 1,\
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PROFTAG_MASK_SHIFT)
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#define PROFTAG_MATCH_SHIFT (0)
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#define PROFTAG_MATCH_MASK GENMASK(PROFTAG_MATCH_SHIFT + 1,\
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PROFTAG_MATCH_SHIFT)
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/* FEAC */
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#define FEAC_SCALING_FILTER_SEL_SHIFT (2)
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#define FEAC_SCALING_FILTER_SEL_MASK GENMASK(FEAC_SCALING_FILTER_SEL_SHIFT \
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+ 0, \
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FEAC_SCALING_FILTER_SEL_SHIFT)
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#define FEAC_SCALING_FILTER_EN_SHIFT (1)
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#define FEAC_SCALING_FILTER_EN BIT(FEAC_SCALING_FILTER_EN_SHIFT)
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#define FEAC_SCALING_FILTER_EN_MASK GENMASK(FEAC_SCALING_FILTER_EN_SHIFT \
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+ 0, \
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FEAC_SCALING_FILTER_EN_SHIFT)
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#define FEAC_WR_BEAT_FILTER_SEL_SHIFT (29)
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#define FEAC_WR_BEAT_FILTER_SEL_MASK GENMASK(FEAC_WR_BEAT_FILTER_SEL_SHIFT \
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+ 0, \
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FEAC_WR_BEAT_FILTER_SEL_SHIFT)
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#define FEAC_WR_BEAT_FILTER_EN_SHIFT (28)
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#define FEAC_WR_BEAT_FILTER_EN_MASK GENMASK(FEAC_WR_BEAT_FILTER_EN_SHIFT \
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+ 0, \
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FEAC_WR_BEAT_FILTER_EN_SHIFT)
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#define FEAC_WR_BEAT_FILTER_EN BIT(FEAC_WR_BEAT_FILTER_EN_SHIFT)
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#define FEAC_WR_BYTE_FILTER_SEL_SHIFT (6)
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#define FEAC_WR_BYTE_FILTER_SEL_MASK GENMASK(FEAC_WR_BYTE_FILTER_SEL_SHIFT \
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+ 0, \
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FEAC_WR_BYTE_FILTER_SEL_SHIFT)
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#define FEAC_WR_BYTE_FILTER_EN_SHIFT (5)
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#define FEAC_WR_BYTE_FILTER_EN_MASK GENMASK(FEAC_WR_BYTE_FILTER_EN_SHIFT \
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+ 0, \
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FEAC_WR_BYTE_FILTER_EN_SHIFT)
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#define FEAC_WR_BYTE_FILTER_EN BIT(FEAC_WR_BYTE_FILTER_EN_SHIFT)
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#define FEAC_RD_BEAT_FILTER_SEL_SHIFT (4)
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#define FEAC_RD_BEAT_FILTER_SEL_MASK GENMASK(FEAC_RD_BEAT_FILTER_SEL_SHIFT \
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+ 0, \
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FEAC_RD_BEAT_FILTER_SEL_SHIFT)
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#define FEAC_RD_BEAT_FILTER_EN_SHIFT (3)
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#define FEAC_RD_BEAT_FILTER_EN_MASK GENMASK(FEAC_RD_BEAT_FILTER_EN_SHIFT \
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+ 0, \
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FEAC_RD_BEAT_FILTER_EN_SHIFT)
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#define FEAC_RD_BEAT_FILTER_EN BIT(FEAC_RD_BEAT_FILTER_EN_SHIFT)
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#define FEAC_RD_BYTE_FILTER_SEL_SHIFT (2)
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#define FEAC_RD_BYTE_FILTER_SEL_MASK GENMASK(FEAC_RD_BYTE_FILTER_SEL_SHIFT \
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+ 0, \
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FEAC_RD_BYTE_FILTER_SEL_SHIFT)
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#define FEAC_RD_BYTE_FILTER_EN_SHIFT (1)
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#define FEAC_RD_BYTE_FILTER_EN_MASK GENMASK(FEAC_RD_BYTE_FILTER_EN_SHIFT \
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+ 0, \
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FEAC_RD_BYTE_FILTER_EN_SHIFT)
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#define FEAC_RD_BYTE_FILTER_EN BIT(FEAC_RD_BYTE_FILTER_EN_SHIFT)
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#define FEAC_ADDR_LOWER_MATCH_SHIFT (0)
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#define FEAC_ADDR_LOWER_MATCH_MASK GENMASK(FEAC_ADDR_LOWER_MATCH_SHIFT \
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+31, \
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FEAC_ADDR_LOWER_MATCH_SHIFT)
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#define FEAC_ADDR_LOWER_MASK_SHIFT (0)
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#define FEAC_ADDR_LOWER_MASK_MASK GENMASK(FEAC_ADDR_LOWER_MASK_SHIFT \
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+31, \
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FEAC_ADDR_LOWER_MASK_SHIFT)
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#define FEAC_ADDR_UPPER_MATCH_SHIFT (0)
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#define FEAC_ADDR_UPPER_MATCH_MASK GENMASK(FEAC_ADDR_UPPER_MATCH_SHIFT \
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+4, \
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FEAC_ADDR_UPPER_MATCH_SHIFT)
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#define FEAC_ADDR_UPPER_MASK_SHIFT (4)
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#define FEAC_ADDR_UPPER_MASK_MASK GENMASK(FEAC_ADDR_UPPER_MASK_SHIFT \
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+4, \
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FEAC_ADDR_UPPER_MASK_SHIFT)
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/* BEAC */
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#define BEAC_PROFTAG_MASK_SHIFT (14)
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#define BEAC_PROFTAG_MASK_MASK GENMASK(BEAC_PROFTAG_MASK_SHIFT + 1,\
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BEAC_PROFTAG_MASK_SHIFT)
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#define BEAC_PROFTAG_MATCH_SHIFT (12)
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#define BEAC_PROFTAG_MATCH_MASK GENMASK(BEAC_PROFTAG_MATCH_SHIFT + 1,\
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BEAC_PROFTAG_MATCH_SHIFT)
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#define BEAC_MC_PROFTAG_SHIFT (1)
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#define BEAC_MC_PROFTAG_MASK GENMASK(BEAC_MC_PROFTAG_SHIFT + 1,\
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BEAC_MC_PROFTAG_SHIFT)
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#define BEAC_WR_BEAT_FILTER_SEL_SHIFT (6)
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#define BEAC_WR_BEAT_FILTER_SEL_MASK GENMASK(BEAC_WR_BEAT_FILTER_SEL_SHIFT \
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+ 0, \
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BEAC_WR_BEAT_FILTER_SEL_SHIFT)
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#define BEAC_WR_BEAT_FILTER_EN_SHIFT (5)
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#define BEAC_WR_BEAT_FILTER_EN_MASK GENMASK(BEAC_WR_BEAT_FILTER_EN_SHIFT \
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+ 0, \
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BEAC_WR_BEAT_FILTER_EN_SHIFT)
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||
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|
#define BEAC_WR_BEAT_FILTER_EN BIT(BEAC_WR_BEAT_FILTER_EN_SHIFT)
|
||
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|
#define BEAC_RD_BEAT_FILTER_SEL_SHIFT (4)
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||
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|
#define BEAC_RD_BEAT_FILTER_SEL_MASK GENMASK(BEAC_RD_BEAT_FILTER_SEL_SHIFT \
|
||
|
|
+ 0, \
|
||
|
|
BEAC_RD_BEAT_FILTER_SEL_SHIFT)
|
||
|
|
#define BEAC_RD_BEAT_FILTER_EN_SHIFT (3)
|
||
|
|
#define BEAC_RD_BEAT_FILTER_EN_MASK GENMASK(BEAC_RD_BEAT_FILTER_EN_SHIFT \
|
||
|
|
+ 0, \
|
||
|
|
BEAC_RD_BEAT_FILTER_EN_SHIFT)
|
||
|
|
#define BEAC_RD_BEAT_FILTER_EN BIT(BEAC_RD_BEAT_FILTER_EN_SHIFT)
|
||
|
|
#define BEAC_ADDR_LOWER_MATCH_SHIFT (0)
|
||
|
|
#define BEAC_ADDR_LOWER_MATCH_MASK GENMASK(BEAC_ADDR_LOWER_MATCH_SHIFT \
|
||
|
|
+31, \
|
||
|
|
BEAC_ADDR_LOWER_MATCH_SHIFT)
|
||
|
|
#define BEAC_ADDR_LOWER_MASK_SHIFT (0)
|
||
|
|
#define BEAC_ADDR_LOWER_MASK_MASK GENMASK(BEAC_ADDR_LOWER_MASK_SHIFT \
|
||
|
|
+31, \
|
||
|
|
BEAC_ADDR_LOWER_MASK_SHIFT)
|
||
|
|
#define BEAC_ADDR_UPPER_MATCH_SHIFT (0)
|
||
|
|
#define BEAC_ADDR_UPPER_MATCH_MASK GENMASK(BEAC_ADDR_UPPER_MATCH_SHIFT \
|
||
|
|
+4, \
|
||
|
|
BEAC_ADDR_UPPER_MATCH_SHIFT)
|
||
|
|
#define BEAC_ADDR_UPPER_MASK_SHIFT (4)
|
||
|
|
#define BEAC_ADDR_UPPER_MASK_MASK GENMASK(BEAC_ADDR_UPPER_MASK_SHIFT \
|
||
|
|
+4, \
|
||
|
|
BEAC_ADDR_UPPER_MASK_SHIFT)
|
||
|
|
/* TRP */
|
||
|
|
#define TRP_SCID_MATCH_SHIFT (0)
|
||
|
|
#define TRP_SCID_MATCH_MASK GENMASK(TRP_SCID_MATCH_SHIFT + 4,\
|
||
|
|
TRP_SCID_MATCH_SHIFT)
|
||
|
|
#define TRP_SCID_MASK_SHIFT (8)
|
||
|
|
#define TRP_SCID_MASK_MASK GENMASK(TRP_SCID_MASK_SHIFT + 4,\
|
||
|
|
TRP_SCID_MASK_SHIFT)
|
||
|
|
#define TRP_WAY_ID_MATCH_SHIFT (16)
|
||
|
|
#define TRP_WAY_ID_MATCH_MASK GENMASK(TRP_WAY_ID_MATCH_SHIFT + 3,\
|
||
|
|
TRP_WAY_ID_MATCH_SHIFT)
|
||
|
|
#define TRP_WAY_ID_MASK_SHIFT (20)
|
||
|
|
#define TRP_WAY_ID_MASK_MASK GENMASK(TRP_WAY_ID_MASK_SHIFT + 3,\
|
||
|
|
TRP_WAY_ID_MASK_SHIFT)
|
||
|
|
#define TRP_PROFTAG_MATCH_SHIFT (24)
|
||
|
|
#define TRP_PROFTAG_MATCH_MASK GENMASK(TRP_PROFTAG_MATCH_SHIFT + 1,\
|
||
|
|
TRP_PROFTAG_MATCH_SHIFT)
|
||
|
|
#define TRP_PROFTAG_MASK_SHIFT (28)
|
||
|
|
#define TRP_PROFTAG_MASK_MASK GENMASK(TRP_PROFTAG_MASK_SHIFT + 1,\
|
||
|
|
TRP_PROFTAG_MASK_SHIFT)
|
||
|
|
|
||
|
|
#define TRP_SCID_STATUS_ACTIVE_SHIFT (0)
|
||
|
|
#define TRP_SCID_STATUS_ACTIVE_MASK GENMASK( \
|
||
|
|
TRP_SCID_STATUS_ACTIVE_SHIFT \
|
||
|
|
+ 0, \
|
||
|
|
TRP_SCID_STATUS_ACTIVE_SHIFT)
|
||
|
|
#define TRP_SCID_STATUS_DEACTIVE_SHIFT (1)
|
||
|
|
#define TRP_SCID_STATUS_CURRENT_CAP_SHIFT (16)
|
||
|
|
#define TRP_SCID_STATUS_CURRENT_CAP_MASK GENMASK( \
|
||
|
|
TRP_SCID_STATUS_CURRENT_CAP_SHIFT \
|
||
|
|
+ 14, \
|
||
|
|
TRP_SCID_STATUS_CURRENT_CAP_SHIFT)
|
||
|
|
|
||
|
|
#define ADDR_LOWER_MASK (0xFFFFFFFF)
|
||
|
|
#define ADDR_UPPER_MASK (0xF00000000)
|
||
|
|
#define ADDR_UPPER_SHIFT (32)
|
||
|
|
#define MAJOR_VER_MASK (0xFF000000)
|
||
|
|
#define BRANCH_MASK (0x00FF0000)
|
||
|
|
#define MINOR_MASK (0x0000FF00)
|
||
|
|
#define LLCC_VERSION_1 (0x01010200)
|
||
|
|
#define LLCC_VERSION_2 (0x02000000)
|
||
|
|
#define LLCC_VERSION_3 (0x03000000)
|
||
|
|
#define LLCC_VERSION_4 (0x04000000)
|
||
|
|
#define LLCC_VERSION_5 (0x05000000)
|
||
|
|
#define MAJOR_REV_NO(v) ((v & MAJOR_VER_MASK) >> 24)
|
||
|
|
#define BRANCH_NO(v) ((v & BRANCH_MASK) >> 16)
|
||
|
|
#define MINOR_NO(v) ((v & MINOR_MASK) >> 8)
|
||
|
|
#define REV_0 (0x0)
|
||
|
|
#define REV_1 (0x1)
|
||
|
|
#define REV_2 (0x2)
|
||
|
|
#define REV_5 (0x5)
|
||
|
|
#define BANK_OFFSET (0x80000)
|
||
|
|
|
||
|
|
#endif /* _SOC_QCOM_LLCC_PERFMON_H_ */
|