36 lines
1,021 B
C
36 lines
1,021 B
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_KHAJE_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_KHAJE_H
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/* GPU_CC clocks */
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#define GPU_CC_AHB_CLK 0
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#define GPU_CC_CRC_AHB_CLK 1
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#define GPU_CC_CX_GFX3D_CLK 2
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#define GPU_CC_CX_GFX3D_SLV_CLK 3
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#define GPU_CC_CX_GMU_CLK 4
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#define GPU_CC_CX_SNOC_DVM_CLK 5
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#define GPU_CC_CXO_AON_CLK 6
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#define GPU_CC_CXO_CLK 7
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#define GPU_CC_GMU_CLK_SRC 8
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#define GPU_CC_GX_CXO_CLK 9
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#define GPU_CC_GX_GFX3D_CLK 10
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#define GPU_CC_GX_GFX3D_CLK_SRC 11
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#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 12
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#define GPU_CC_PLL0 13
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#define GPU_CC_PLL0_OUT_MAIN 14
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#define GPU_CC_PLL1 15
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#define GPU_CC_SLEEP_CLK 16
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/* GPU_CC resets */
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#define GPUCC_GPU_CC_CX_BCR 0
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#define GPUCC_GPU_CC_GFX3D_AON_BCR 1
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#define GPUCC_GPU_CC_GMU_BCR 2
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#define GPUCC_GPU_CC_GX_BCR 3
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#define GPUCC_GPU_CC_XO_BCR 4
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#endif
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