119 lines
2.9 KiB
C
119 lines
2.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/thermal/thermal.h>
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#ifndef _DT_BINDINGS_QTI_THERMAL_H
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#define _DT_BINDINGS_QTI_THERMAL_H
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#define THERMAL_MAX_LIMIT (THERMAL_NO_LIMIT - 1)
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#define AGGREGATE_COEFF_VALUE 0
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#define AGGREGATE_MAX_VALUE 1
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#define AGGREGATE_MIN_VALUE 2
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#define QMI_PA 0
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#define QMI_PA_1 1
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#define QMI_PA_2 2
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#define QMI_QFE_PA_0 3
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#define QMI_QFE_WTR_0 4
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#define QMI_MODEM_TSENS 5
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#define QMI_QFE_MMW_0 6
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#define QMI_QFE_MMW_1 7
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#define QMI_QFE_MMW_2 8
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#define QMI_QFE_MMW_3 9
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#define QMI_XO_THERM 10
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#define QMI_QFE_PA_MDM 11
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#define QMI_QFE_PA_WTR 12
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#define QMI_QFE_MMW_STREAMER_0 13
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#define QMI_QFE_MMW_0_MOD 14
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#define QMI_QFE_MMW_1_MOD 15
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#define QMI_QFE_MMW_2_MOD 16
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#define QMI_QFE_MMW_3_MOD 17
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#define QMI_QFE_RET_PA_0 18
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#define QMI_QFE_WTR_PA_0 19
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#define QMI_QFE_WTR_PA_1 20
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#define QMI_QFE_WTR_PA_2 21
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#define QMI_QFE_WTR_PA_3 22
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#define QMI_SYS_THERM_1 23
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#define QMI_SYS_THERM_2 24
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#define QMI_MODEM_TSENS_1 25
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#define QMI_MMW_PA1 26
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#define QMI_MMW_PA2 27
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#define QMI_MMW_PA3 28
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#define QMI_SDR_MMW 29
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#define QMI_QTM_THERM 30
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#define QMI_BCL_WARN 31
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#define QMI_SDR0_PA0 32
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#define QMI_SDR0_PA1 33
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#define QMI_SDR0_PA2 34
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#define QMI_SDR0_PA3 35
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#define QMI_SDR0_PA4 36
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#define QMI_SDR0_PA5 37
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#define QMI_SDR0 38
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#define QMI_SDR1_PA0 39
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#define QMI_SDR1_PA1 40
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#define QMI_SDR1_PA2 41
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#define QMI_SDR1_PA3 42
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#define QMI_SDR1_PA4 43
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#define QMI_SDR1_PA5 44
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#define QMI_SDR1 45
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#define QMI_MMW0 46
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#define QMI_MMW1 47
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#define QMI_MMW2 48
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#define QMI_MMW3 49
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#define QMI_MMW_IFIC0 50
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#define QMI_SUB1_MODEM_CFG 51
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#define QMI_SUB1_LTE_CC 52
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#define QMI_SUB1_MCG_FR1_CC 53
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#define QMI_SUB1_MCG_FR2_CC 54
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#define QMI_SUB1_SCG_FR1_CC 55
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#define QMI_SUB1_SCG_FR2_CC 56
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#define QMI_SUB2_MODEM_CFG 57
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#define QMI_SUB2_LTE_CC 58
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#define QMI_SUB2_MCG_FR1_CC 59
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#define QMI_SUB2_MCG_FR2_CC 60
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#define QMI_SUB2_SCG_FR1_CC 61
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#define QMI_SUB2_SCG_FR2_CC 62
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#define QMI_NSP_ISENSE_TRIM 63
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#define QMI_EPM0 64
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#define QMI_EPM1 65
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#define QMI_EPM2 66
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#define QMI_EPM3 67
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#define QMI_EPM4 68
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#define QMI_EPM5 69
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#define QMI_EPM6 70
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#define QMI_EPM7 71
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#define QMI_SDR0_PA 72
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#define QMI_SDR1_PA 73
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#define QMI_SDR2_PA 74
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#define QMI_SDR3_PA 75
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#define QMI_SDR4_PA 76
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#define QMI_SDR5_PA 77
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#define QMI_SDR6_PA 78
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#define QMI_SDR7_PA 79
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#define QMI_SDR2 80
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#define QMI_SDR3 81
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#define QMI_SDR4 82
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#define QMI_SDR5 83
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#define QMI_SDR6 84
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#define QMI_SDR7 85
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#define QMI_RF_CAL 86
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#define QMI_MODEM_CFG 87
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#define QMI_LTE_CC 88
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#define QMI_MCG_FR1_CC 89
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#define QMI_MCG_FR2_CC 90
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#define QMI_SCG_FR1_CC 91
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#define QMI_SCG_FR2_CC 92
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#define QMI_MODEM_INST_ID 0x0
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#define QMI_ADSP_INST_ID 0x1
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#define QMI_CDSP_INST_ID 0x43
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#define QMI_CDSP1_INST_ID 0x44
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#define QMI_SLPI_INST_ID 0x53
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#define QMI_MODEM_NR_INST_ID 0x64
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#endif
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