* ARM System MMU Architecture Implementation ARM SoCs may contain an implementation of the ARM System Memory Management Unit Architecture, which can be used to provide 1 or 2 stages of address translation to bus masters external to the CPU. The SMMU may also raise interrupts in response to various fault conditions. ** System MMU required properties: - compatible : Should be one of: "arm,smmu-v1" "arm,smmu-v2" "arm,mmu-400" "arm,mmu-401" "arm,mmu-500" "cavium,smmu-v2" "qcom,qsmmu-v500" "qcom,adreno-smmu" "qcom,smmu-v2" "qcom,virt-smmu" depending on the particular implementation and/or the version of the architecture implemented. Qcom SoCs must contain, as below, SoC-specific compatibles along with "qcom,smmu-v2": "qcom,msm8996-smmu-v2", "qcom,smmu-v2", "qcom,sdm845-smmu-v2", "qcom,smmu-v2". Qcom SoCs implementing "arm,mmu-500" must also include, as below, SoC-specific compatibles: "qcom,sdm845-smmu-500", "arm,mmu-500" "qcom,virt-smmu" is a subtype of "qcom,qsmmu-v500" which only supports access to the set of registers required by the arm specificiation. None of the additional registers normally present in qcom,qsmmu-v500 are supported currently. - reg : Base address and size of the SMMU. - reg-names : For the "qcom,qsmmu-v500" device "tcu-base" is expected. - #global-interrupts : The number of global interrupts exposed by the device. - interrupts : Interrupt list, with the first #global-irqs entries corresponding to the global interrupts and any following entries corresponding to context interrupts, specified in order of their indexing by the SMMU. For SMMUv2 implementations, there must be exactly one interrupt per context bank. In the case of a single, combined interrupt, it must be listed multiple times. - #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a value of 1, each IOMMU specifier represents a distinct stream ID emitted by that device into the relevant SMMU. SMMUs with stream matching support and complex masters may use a value of 2, where the second cell of the IOMMU specifier represents an SMR mask to combine with the ID in the first cell. Care must be taken to ensure the set of matched IDs does not result in conflicts. ** System MMU optional properties: - dma-coherent : Present if page table walks made by the SMMU are cache coherent with the CPU. NOTE: this only applies to the SMMU itself, not masters connected upstream of the SMMU. - calxeda,smmu-secure-config-access : Enable proper handling of buggy implementations that always use secure access to SMMU configuration registers. In this case non-secure aliases of secure registers have to be used during SMMU configuration. - stream-match-mask : For SMMUs supporting stream matching and using #iommu-cells = <1>, specifies a mask of bits to ignore when matching stream IDs (e.g. this may be programmed into the SMRn.MASK field of every stream match register used). For cases where it is desirable to ignore some portion of every Stream ID (e.g. for certain MMU-500 configurations given globally unique input IDs). This property is not valid for SMMUs using stream indexing, or using stream matching with #iommu-cells = <2>, and may be ignored if present in such cases. - clock-names: List of the names of clocks input to the device. The required list depends on particular implementation and is as follows: - for "qcom,smmu-v2": - "bus": clock required for downstream bus access and for the smmu ptw, - "iface": clock required to access smmu's registers through the TCU's programming interface. - unspecified for other implementations. - clocks: Specifiers for all clocks listed in the clock-names property, as per generic clock bindings. - power-domains: Specifiers for power domains required to be powered on for the SMMU to operate, as per generic power domain bindings. - attach-impl-defs : global registers to program at device attach time. This should be a list of 2-tuples of the format: . - qcom,fatal-asf : Enable BUG_ON for address size faults. Some hardware requires special fixups to recover from address size faults. Rather than applying the fixups just BUG since address size faults are due to a fundamental programming error from which we don't care about recovering anyways. - qcom,skip-init : Disable resetting configuration for all context banks during device reset. This is useful for targets where some context banks are dedicated to other execution environments outside of Linux and those other EEs are programming their own stream match tables, SCTLR, etc. Without setting this option we will trample on their configuration. - qcom,use-3-lvl-tables: Some hardware configurations may not be optimized for using a four level page table configuration. Set to use a three level page table instead. - qcom,context-fault-retry: Retry iommu faults after a tlb invalidate, if stall-on-fault is enabled. - qcom,no-asid-retention: Some hardware may lose internal state for asid after retention. No cache invalidation operations involving asid may be used. - qcom,split-tables: Some hardware configurations can easily use a model where the I/O virtual address space for a domain can be split into two symmetric portions, and clients can manage each portion. Set for hardware that supports this model, and requires this feature. - qcom,actlr: An array of . Any sid X for which X&~mask==sid will be programmed with the given actlr-setting. -qcom,disable-atos: Some hardware may not have full support for atos debugging in tandem with other features like power collapse. - (%s)-supply : Phandle of the regulator that should be powered on during SMMU register access. (%s) is a string from the qcom,regulator-names property. - qcom,regulator-names : List of strings to use with the (%s)-supply property. - interconnects: Pairs of phandles and interconnect provider specifier to denote the edge source and destination ports of the interconnect path. For more information, please see bindings/interconnect/interconnect.txt - qcom,active-only: Boolean property which denotes that interconnect votes should be maintained while the CPUSS is awake (active context). The absence of this property makes it so that interconnect votes will be maintained irrespective of the CPUSS' state (awake or asleep). - qcom,num-context-banks-override: Optional integer. Should be set if the hypervisor virtualization is disabled for debugging purposes. When this is done, some context banks managed by hypervisor become visible to HLOS, but should not be accessed. - qcom,num-smr-override: Optional integer. See qcom,num-context-banks-override. - qcom,multi-match-handoff-smr: Optional property. Should be included if one handoff SMR matches multiple SMRs. ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : A list of phandles to device nodes representing bus masters for which the SMMU can provide a translation and their corresponding Stream IDs. Each device node linked from this list must have a "#stream-id-cells" property, indicating the number of Stream ID arguments associated with its phandle. ** Additional properties for Iommu Clients: - qcom,iommu-dma: Optional, String. Can be one of "bypass", "fastmap", "atomic", "disabled". --- "default": Standard iommu translation behavior. The iommu framework will automatically create a domain for the client. iommu and DMA apis may not be called in atomic context. --- "bypass": DMA APIs will use 1-to-1 translation between dma_addr and phys_addr. Allows using iommu and DMA apis in atomic context. --- "fastmap": DMA APIs will run faster, but use several orders of magnitude more memory. Also allows using iommu and DMA apis in atomic context. --- "atomic": Allows using iommu and DMA apis in atomic context. --- "disabled": The iommu client is responsible for allocating an iommu domain, as well as calling iommu_map to create the desired mappings. - qcom,iommu-faults: Optional, List of Strings. The SCTLR register setting which affect iommu faults handling. Any combination of the below strings may be used. Mutliple values are accepted. --- "default": Any faults are treated as fatal errors. --- "no-CFRE": Iommu faults do not return an abort to the client hardware. --- "non-fatal": Iommu faults do not trigger a kernel panic. --- "stall-disable": Iommu faults do not stall the client while the fault interrupt is being handled. - qcom,iommu-vmid: Optional, Int. An identifier indicating the security state of the client. - qcom,iommu-pagetable: Optional, String. Enables coherency for the IOMMU device, but not for the Client. --- "default": Pagetable coherency defaults to the coherency setting of the IOMMU device. --- "coherent" Pagetables are io-coherent. --- "LLC" Pagetables may be saved in the system cache. Should not be used if the IOMMU device is io-coherent. --- "LLC_NWA" Pagetables may be saved in the system cache is used, and write-allocate hint is disabled. Should not be used if the IOMMU device is io-coherent. - qcom,iommu-earlymap: Optional, Bool. Support creating mappings in the page-table before Stage 1 translation is enabled. - qcom,iommu-dma-addr-pool: Optional, tuple of
. Defaults to <0, SZ_4G> if not present. Indicates the range of addresses that the dma layer will use. - qcom,iommu-geometry: Optional, tuple of
. Defaults to <0, SZ_4G> if not present. Indicates the available IOVA space when the qcom,iommu-dma property is set to "fastmap". The new space created will be a superset of the IOVA range which was created through the qcom,iommu-dma-addr-pool DT property. - qcom,iommu-msi-size: Optional, Int. Indicates the amount of space--in bytes--that must be reserved from the client's total IOVA space for mapping MSI registers when the qcom,iommu-dma property is set to "fastmap". -qcom,iommu-defer-smr-config: Optional, Bool. Indicates that the SMRs for the client should not be programmed when the client device is attaching to the SMMU, but when the client's device driver requests it at a later point in time when the client is ready for DMA transfers. ** Examples: /* SMMU with stream matching or stream indexing */ smmu1: iommu { compatible = "arm,smmu-v1"; reg = <0xba5e0000 0x10000>; #global-interrupts = <2>; interrupts = <0 32 4>, <0 33 4>, <0 34 4>, /* This is the first context interrupt */ <0 35 4>, <0 36 4>, <0 37 4>; #iommu-cells = <1>; }; /* device with two stream IDs, 0 and 7 */ master1 { iommus = <&smmu1 0>, <&smmu1 7>; }; /* SMMU with stream matching */ smmu2: iommu { ... #iommu-cells = <2>; }; /* device with stream IDs 0 and 7 */ master2 { iommus = <&smmu2 0 0>, <&smmu2 7 0>; }; /* device with stream IDs 1, 17, 33 and 49 */ master3 { iommus = <&smmu2 1 0x30>; }; /* ARM MMU-500 with 10-bit stream ID input configuration */ smmu3: iommu { compatible = "arm,mmu-500", "arm,smmu-v2"; ... #iommu-cells = <1>; /* always ignore appended 5-bit TBU number */ stream-match-mask = 0x7c00; }; bus { /* bus whose child devices emit one unique 10-bit stream ID each, but may master through multiple SMMU TBUs */ iommu-map = <0 &smmu3 0 0x400>; ... }; /* Qcom's arm,smmu-v2 implementation */ smmu4: iommu@d00000 { compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; reg = <0xd00000 0x10000>; #global-interrupts = <1>; interrupts = , , ; #iommu-cells = <1>; power-domains = <&mmcc MDSS_GDSC>; clocks = <&mmcc SMMU_MDP_AXI_CLK>, <&mmcc SMMU_MDP_AHB_CLK>; clock-names = "bus", "iface"; }; * Qualcomm Technologies, Inc. MMU-500 TBU Device The qcom,qsmmu-v500 device implements a number of register regions containing debug functionality. Each register region maps to a separate tbu from the arm mmu-500 implementation. ** TBU/QTB required properties: - compatible : Should be one of: "qcom,qsmmuv500-tbu" "qcom,qtb500" can be used in conjunction with "qcom,qsmmuv500-tbu", as the QTB500 is an implementation of a TBU with different features/enhancements than a regular TBU. - reg : Base address and size. -qcom,stream-id-range: Pair of values describing the smallest supported stream-id and the size of the entire set. -qcom,iova-width: The maximum number of bits that a TBU can support for IOVAs. ** TBU/QTB optional properties: -qcom,opt-out-tbu-halting: Allow certain TBUs to opt-out from being halted for the ATOS operation to proceed. Halting certain TBUs would cause considerable impact to the system such as deadlocks on demand. Such TBUs can be opted out to be halted from software. ** QTB required properties: -interconnects: The interconnect path to vote for prior to accessing the QTB registers. -qcom,num-qtb-ports: Specifies the number of ports that a QTB has for incoming transactions. ** QTB optional properties: -qcom,no-qtb-atos-halt: Specifies that a TBU does not need to be halted for performing ATOS debugging. Example: TBU: smmu { compatible = "qcom,qsmmu-v500"; tbu@0x1000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x1000 0x1000>; qcom,stream-id-range = <0x800 0x400>; qcom,iova-width = <36>; }; }; QTB: smmu { compatible = "qcom,qsmmu-v500"; qtb@0x1000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; regs = <0x1000 0x1000>; qcom,stream-id-range = <0x800 0x400>; qcom,iova-width = <36>; interconnects = <&system_noc MASTER_A1NOC_SNOC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <1>; }; };