#include #include &soc { usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; reg = <0xa600000 0x100000>; reg-names = "core_base"; #address-cells = <1>; #size-cells = <1>; ranges; dma-ranges; interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, <&pdc 138 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_RISING>; interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", "ss_phy_irq", "dm_hs_phy_irq"; qcom,use-pdc-interrupts; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>, <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, <&gcc GCC_SYS_NOC_USB_AXI_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "noc_aggr_clk", "noc_aggr_north_clk", "noc_aggr_south_clk", "noc_sys_clk"; resets = <&gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; qcom,host-poweroff-in-pm-suspend; status = "disabled"; dwc3@a600000 { compatible = "snps,dwc3"; reg = <0xa600000 0xd93c>; iommus = <&apps_smmu 0x0820 0x0>; qcom,iommu-dma = "bypass"; interrupts = ; usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy0>; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,ssp-u3-u0-quirk; snps,is-utmi-l1-suspend; snps,usb2-gadget-lpm-disable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; tx-fifo-resize; maximum-speed = "super-speed-plus"; dr_mode = "otg"; usb-role-switch; }; }; /* Primary USB port related High Speed PHY */ usb2_phy0: hsphy@88e5000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x088e5000 0x120>; reg-names = "hsusb_phy_base"; vdd-supply = <&L5A0>; vdda18-supply = <&L7A0>; vdda33-supply = <&L13A0>; qcom,vdd-voltage-level = <0 912000 912000>; clocks = <&dummycc RPMH_CXO_CLK>; clock-names = "ref_clk_src"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x63 0x6c /* override_x0 */ 0xC8 0x70 /* override_x1 */ 0x17 0x74>; /* override x2 */ status = "disabled"; }; /* Primary USB port related USB4-USB3-DP PHY */ usb_qmp_dp_phy0: ssphy@88eb000 { compatible = "qcom,usb-ssphy-qmp-dp-combo"; reg = <0x88eb000 0x4000>; reg-names = "qmp_phy_base"; vdd-supply = <&L5A0>; qcom,vdd-voltage-level = <0 912000 912000>; qcom,vdd-max-load-uA = <47000>; core-supply = <&L3A0>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&dummycc RPMH_CXO_CLK>, <&gcc GCC_USB4_EUD_CLKREF_CLK>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk"; resets = <&gcc GCC_USB4_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "global_phy_reset", "phy_reset"; qcom,qmp-phy-reg-offset = ; qcom,qmp-phy-init-seq = /* */ ; status = "disabled"; }; usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; usb1: ssusb@a800000 { compatible = "qcom,dwc-usb3-msm"; reg = <0xa800000 0x100000>; reg-names = "core_base"; #address-cells = <1>; #size-cells = <1>; ranges; dma-ranges; interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_RISING>, <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, <&pdc 136 IRQ_TYPE_LEVEL_HIGH>, <&pdc 13 IRQ_TYPE_EDGE_RISING>; interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", "ss_phy_irq", "dm_hs_phy_irq"; qcom,use-pdc-interrupts; USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>; clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&gcc GCC_USB30_SEC_SLEEP_CLK>, <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, <&gcc GCC_SYS_NOC_USB_AXI_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "noc_aggr_clk", "noc_aggr_north_clk", "noc_aggr_south_clk", "noc_sys_clk"; resets = <&gcc GCC_USB30_SEC_BCR>; reset-names = "core_reset"; qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; qcom,host-poweroff-in-pm-suspend; qcom,default-mode-host; status = "disabled"; dwc3@a800000 { compatible = "snps,dwc3"; reg = <0xa800000 0xd93c>; iommus = <&apps_smmu 0x0860 0x0>; qcom,iommu-dma = "bypass"; interrupts = ; usb-phy = <&usb2_phy1>, <&usb_qmp_dp_phy1>; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,ssp-u3-u0-quirk; snps,is-utmi-l1-suspend; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,usb2-gadget-lpm-disable; tx-fifo-resize; maximum-speed = "super-speed-plus"; dr_mode = "otg"; usb-role-switch; }; }; /* Secondary USB port related High Speed PHY */ usb2_phy1: hsphy@8902000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x08902000 0x120>; reg-names = "hsusb_phy_base"; vdd-supply = <&L1C0>; vdda18-supply = <&L7C0>; vdda33-supply = <&L2C0>; qcom,vdd-voltage-level = <0 912000 912000>; clocks = <&dummycc RPMH_CXO_CLK>; clock-names = "ref_clk_src"; resets = <&gcc GCC_USB2_PHY_SEC_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x63 0x6c /* override_x0 */ 0xC8 0x70 /* override_x1 */ 0x17 0x74>; /* override x2 */ status = "disabled"; }; /* Secondary USB port related USB4-USB3-DP PHY */ usb_qmp_dp_phy1: ssphy@8903000 { compatible = "qcom,usb-ssphy-qmp-dp-combo"; reg = <0x8903000 0x4000>; reg-names = "qmp_phy_base"; vdd-supply = <&L1C0>; qcom,vdd-voltage-level = <0 912000 912000>; qcom,vdd-max-load-uA = <47000>; core-supply = <&L4C0>; clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, <&gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <&usb3_uni_phy_sec_gcc_usb30_pipe_clk>, <&dummycc RPMH_CXO_CLK>, <&gcc GCC_USB4_CLKREF_CLK>, <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk"; resets = <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_SEC_BCR>; reset-names = "global_phy_reset", "phy_reset"; qcom,qmp-phy-reg-offset = ; qcom,qmp-phy-init-seq = /* */ ; status = "disabled"; }; /* Tertiary USB port related controller */ usb2: ssusb@a400000 { compatible = "qcom,dwc-usb3-msm"; reg = <0xa400000 0x100000>; reg-names = "core_base"; #address-cells = <1>; #size-cells = <1>; ranges; dma-ranges; interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, <&pdc 126 IRQ_TYPE_EDGE_RISING>, <&pdc 129 IRQ_TYPE_EDGE_RISING>, <&pdc 128 IRQ_TYPE_EDGE_RISING>, <&pdc 131 IRQ_TYPE_EDGE_RISING>, <&pdc 130 IRQ_TYPE_EDGE_RISING>, <&pdc 133 IRQ_TYPE_EDGE_RISING>, <&pdc 132 IRQ_TYPE_EDGE_RISING>, <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq1", "dm_hs_phy_irq1", "dp_hs_phy_irq2", "dm_hs_phy_irq2", "dp_hs_phy_irq3", "dm_hs_phy_irq3", "ss_phy_irq", "ss_phy_irq1"; qcom,use-pdc-interrupts; USB3_GDSC-supply = <&gcc_usb30_mp_gdsc>; clocks = <&gcc GCC_USB30_MP_MASTER_CLK>, <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, <&gcc GCC_USB30_MP_SLEEP_CLK>, <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, <&gcc GCC_SYS_NOC_USB_AXI_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "noc_aggr_clk", "noc_aggr_north_clk", "noc_aggr_south_clk", "noc_sys_clk"; resets = <&gcc GCC_USB30_MP_BCR>; reset-names = "core_reset"; qcom,core-clk-rate = <200000000>; qcom,host-poweroff-in-pm-suspend; status = "disabled"; dwc3@a400000 { compatible = "snps,dwc3"; reg = <0xa400000 0xd93c>; iommus = <&apps_smmu 0x0800 0x0>; qcom,iommu-dma = "bypass"; interrupts = ; usb-phy = <&usb2_phy2>, <&usb_qmp_phy0>, <&usb2_phy3>, <&usb_qmp_phy1>, <&usb2_phy4>, <&usb_nop_phy>, <&usb2_phy5>, <&usb_nop_phy>; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,ssp-u3-u0-quirk; snps,is-utmi-l1-suspend; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed-plus"; dr_mode = "host"; }; }; /* Tertiary USB port 0 related High Speed PHY */ usb2_phy2: hsphy@88e7000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88e7000 0x120>; reg-names = "hsusb_phy_base"; vdd-supply = <&L5A0>; vdda18-supply = <&L7G0>; vdda33-supply = <&L13A0>; qcom,vdd-voltage-level = <0 912000 912000>; clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; clock-names = "ref_clk_src"; resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x63 0x6c /* override_x0 */ 0xC8 0x70 /* override_x1 */ 0x17 0x74>; /* override x2 */ status = "disabled"; }; /* Tertiary USB port 0 related QMP PHY */ usb_qmp_phy0: ssphy@88ef000 { compatible = "qcom,usb-ssphy-qmp-v2"; reg = <0x88ef000 0x2000>, <0x088ef28c 0x4>; reg-names = "qmp_phy_base", "pcs_clamp_enable_reg"; vdd-supply = <&L5A0>; qcom,vdd-voltage-level = <0 912000 912000>; qcom,vdd-max-load-uA = <47000>; core-supply = <&L3A0>; clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>, <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK_SRC>, <&usb3_uni_phy_mp_gcc_usb30_pipe_0_clk>, <&dummycc RPMH_CXO_CLK>, <&gcc GCC_USB3_MP0_CLKREF_CLK>, <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk"; resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; reset-names = "phy_reset", "phy_phy_reset"; qcom,qmp-phy-reg-offset = ; qcom,qmp-phy-init-seq = /* */ ; status = "disabled"; }; /* Tertiary USB port 1 related High Speed PHY */ usb2_phy3: hsphy@88e8000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88e8000 0x120>; reg-names = "hsusb_phy_base"; vdd-supply = <&L5A0>; vdda18-supply = <&L7G0>; vdda33-supply = <&L13A0>; qcom,vdd-voltage-level = <0 912000 912000>; clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; clock-names = "ref_clk_src"; resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x63 0x6c /* override_x0 */ 0xC8 0x70 /* override_x1 */ 0x17 0x74>; /* override x2 */ status = "disabled"; }; /* Tertiary USB port 1 related QMP PHY */ usb_qmp_phy1: ssphy@88f1000 { compatible = "qcom,usb-ssphy-qmp-v2"; reg = <0x88f1000 0x2000>, <0x088f128c 0x4>; reg-names = "qmp_phy_base", "pcs_clamp_enable_reg"; vdd-supply = <&L5A0>; qcom,vdd-voltage-level = <0 912000 912000>; qcom,vdd-max-load-uA = <47000>; core-supply = <&L3A0>; clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>, <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK_SRC>, <&usb3_uni_phy_mp_gcc_usb30_pipe_1_clk>, <&dummycc RPMH_CXO_CLK>, <&gcc GCC_USB3_MP1_CLKREF_CLK>, <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk"; resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; reset-names = "phy_reset", "phy_phy_reset"; qcom,qmp-phy-reg-offset = ; qcom,qmp-phy-init-seq = /* */ ; status = "disabled"; }; /* Tertiary USB port 2 related High Speed PHY */ usb2_phy4: hsphy@88e9000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88e9000 0x120>; reg-names = "hsusb_phy_base"; vdd-supply = <&L5A0>; vdda18-supply = <&L7G0>; vdda33-supply = <&L13A0>; qcom,vdd-voltage-level = <0 912000 912000>; clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; clock-names = "ref_clk_src"; resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x63 0x6c /* override_x0 */ 0xC8 0x70 /* override_x1 */ 0x17 0x74>; /* override x2 */ status = "disabled"; }; /* Tertiary USB port 3 related High Speed PHY */ usb2_phy5: hsphy@88ea000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88ea000 0x120>; reg-names = "hsusb_phy_base"; vdd-supply = <&L5A0>; vdda18-supply = <&L7G0>; vdda33-supply = <&L13A0>; qcom,vdd-voltage-level = <0 912000 912000>; clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; clock-names = "ref_clk_src"; resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x63 0x6c /* override_x0 */ 0xC8 0x70 /* override_x1 */ 0x17 0x74>; /* override x2 */ status = "disabled"; }; };