#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))

&msm_gpu {
		label = "kgsl-3d0";
		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
		status = "ok";

		reg = <0x5900000 0x90000>,
			<0x5961000 0x800>;
		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc";

		interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "kgsl_3d0_irq";

		qcom,id = <0>;
		qcom,gpu-model = "Adreno610v1";
		qcom,chipid = <0x06010000>;

		qcom,initial-pwrlevel = <6>;

		qcom,ubwc-mode = <1>;
		qcom,min-access-length = <64>;

		/* base addr, size */
		qcom,gpu-qdss-stm = <0xe1c0000 0x40000>;
		#cooling-cells = <2>;

		clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
			<&gpucc GPU_CC_CXO_CLK>,
			<&gcc GCC_BIMC_GPU_AXI_CLK>,
			<&gpucc GPU_CC_AHB_CLK>,
			<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
			<&gpucc GPU_CC_CX_GMU_CLK>,
			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
			<&rpmcc RPM_SMD_QDSS_CLK>,
			<&gpucc GPU_CC_AHB_CLK>,
			<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
			<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;

		clock-names = "core_clk",
				"rbbmtimer_clk",
				"iface_clk",
				"ahb_clk",
				"mem_clk",
				"gmu_clk",
				"smmu_vote",
				"apb_pclk",
				"gpu_cc_ahb",
				"gcc_gpu_memnoc_gfx",
				"gpu_cc_hlos1_vote_gpu_smmu",
				"gcc_gpu_snoc_dvm_gfx";

		interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
		interconnect-names = "gpu_icc_path";

		qcom,bus-table-cnoc =
			<0>,   /* Off */
			<100>; /* On */

		qcom,bus-table-ddr =
			<MHZ_TO_KBPS(0, 8)>,    /* index=0  */
			<MHZ_TO_KBPS(100, 8)>,  /* index=1  */
			<MHZ_TO_KBPS(200, 8)>,  /* index=2  */
			<MHZ_TO_KBPS(300, 8)>,  /* index=3  */
			<MHZ_TO_KBPS(451, 8)>,  /* index=4  */
			<MHZ_TO_KBPS(547, 8)>,  /* index=5  */
			<MHZ_TO_KBPS(681, 8)>,  /* index=6  */
			<MHZ_TO_KBPS(768, 8)>,  /* index=7  */
			<MHZ_TO_KBPS(1017, 8)>, /* index=8  */
			<MHZ_TO_KBPS(1353, 8)>, /* index=9  */
			<MHZ_TO_KBPS(1555, 8)>, /* index=10  */
			<MHZ_TO_KBPS(1804, 8)>; /* index=11  */


		/* GDSC regulator names */
		regulator-names = "vddcx", "vdd";
		/* GDSC oxili regulators */
		vddcx-supply = <&gpu_cx_gdsc>;
		vdd-supply = <&gpu_gx_gdsc>;

		/* CPU latency parameter */
		qcom,pm-qos-active-latency = <422>;
		qcom,pm-qos-wakeup-latency = <422>;

		/* Enable context aware freq. scaling */
		qcom,enable-ca-jump;
		/* Context aware jump busy penalty in us */
		qcom,ca-busy-penalty = <12000>;
		/* Context aware jump target power level */
		qcom,ca-target-pwrlevel = <5>;

		nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
		nvmem-cell-names = "speed_bin", "gaming_bin";

		qcom,gpu-cx-ipeak {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "qcom,gpu-cx-ipeak";

			qcom,gpu-cx-ipeak@0 {
				qcom,gpu-cx-ipeak = <&cx_ipeak_lm 10>;
				qcom,gpu-cx-ipeak-freq = <950000000>;
			};

			qcom,gpu-cx-ipeak@1 {
				qcom,gpu-cx-ipeak = <&cx_ipeak_lm 1>;
				qcom,gpu-cx-ipeak-freq = <900000000>;
			};
		};

		/* ZAP Shader memory */
		zap-shader {
			memory-region = <&pil_gpu_mem>;
		};

		/* GPU Mempools */
		qcom,gpu-mempools {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "qcom,gpu-mempools";

			/* 4K Page Pool configuration */
			qcom,gpu-mempool@0 {
				reg = <0>;
				qcom,mempool-page-size = <4096>;
				qcom,mempool-allocate;
			};
			/* 8K Page Pool configuration */
			qcom,gpu-mempool@1 {
				reg = <1>;
				qcom,mempool-page-size = <8192>;
				qcom,mempool-allocate;
			};
			/* 64K Page Pool configuration */
			qcom,gpu-mempool@2 {
				reg = <2>;
				qcom,mempool-page-size = <65536>;
				qcom,mempool-reserved = <256>;
			};
			/* 1M Page Pool configuration */
			qcom,gpu-mempool@3 {
				reg = <3>;
				qcom,mempool-page-size = <1048576>;
				qcom,mempool-reserved = <32>;
			};
		};

		/* GPU Mempool configuration for low memory SKUs */
		qcom,gpu-mempools-lowmem {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "qcom,gpu-mempools-lowmem";

			/* 4K Page Pool configuration */
			qcom,gpu-mempool@0 {
				reg = <0>;
				qcom,mempool-page-size = <4096>;
				qcom,mempool-allocate;
			};
			/* 8K Page Pool configuration */
			qcom,gpu-mempool@1 {
				reg = <1>;
				qcom,mempool-page-size = <8192>;
				qcom,mempool-allocate;
			};
			/* 64K Page Pool configuration */
			qcom,gpu-mempool@2 {
				reg = <2>;
				qcom,mempool-page-size = <65536>;
				qcom,mempool-allocate;
				qcom,mempool-max-pages = <256>;
			};
			/* 1M Page Pool configuration */
			qcom,gpu-mempool@3 {
				reg = <3>;
				qcom,mempool-page-size = <1048576>;
				qcom,mempool-allocate;
				qcom,mempool-max-pages = <32>;
			};
		};

		/*
		 * Speed-bin zero is default speed bin.
		 * For rest of the speed bins, speed-bin value
		 * is calculated as FMAX/4.8 MHz round up to zero
		 * decimal places plus two margin to account for
		 * clock jitters.
		 */
		qcom,gpu-pwrlevel-bins {
			#address-cells = <1>;
			#size-cells = <0>;

			compatible = "qcom,gpu-pwrlevel-bins";

			qcom,gpu-pwrlevels-0 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <0>;

				qcom,initial-pwrlevel = <6>;
				qcom,ca-target-pwrlevel = <5>;

				/* TURBO_L1 */
				qcom,gpu-pwrlevel@0 {
					reg = <0>;
					qcom,gpu-freq = <980000000>;
					qcom,bus-freq = <11>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
					qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
				};

				/* TURBO */
				qcom,gpu-pwrlevel@1 {
					reg = <1>;
					qcom,gpu-freq = <900000000>;
					qcom,bus-freq = <11>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
					qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
				};

				/* NOM_L1 */
				qcom,gpu-pwrlevel@2 {
					reg = <2>;
					qcom,gpu-freq = <820000000>;
					qcom,bus-freq = <10>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
					qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
				};

				/* NOM */
				qcom,gpu-pwrlevel@3 {
					reg = <3>;
					qcom,gpu-freq = <745000000>;
					qcom,bus-freq = <9>;
					qcom,bus-min = <8>;
					qcom,bus-max = <10>;
					qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
				};

				/* SVS_L1 */
				qcom,gpu-pwrlevel@4 {
					reg = <4>;
					qcom,gpu-freq = <600000000>;
					qcom,bus-freq = <8>;
					qcom,bus-min = <8>;
					qcom,bus-max = <9>;
					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
				};

				/* SVS */
				qcom,gpu-pwrlevel@5 {
					reg = <5>;
					qcom,gpu-freq = <465000000>;
					qcom,bus-freq = <7>;
					qcom,bus-min = <5>;
					qcom,bus-max = <8>;
					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
				};

				/* LOW SVS */
				qcom,gpu-pwrlevel@6 {
					reg = <6>;
					qcom,gpu-freq = <320000000>;
					qcom,bus-freq = <4>;
					qcom,bus-min = <3>;
					qcom,bus-max = <5>;
					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};

				/* XO */
				qcom,gpu-pwrlevel@7 {
					reg = <7>;
					qcom,gpu-freq = <0>;
					qcom,bus-freq = <0>;
					qcom,bus-min = <0>;
					qcom,bus-max = <0>;
					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};
			};

			qcom,gpu-pwrlevels-1 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <206>;

				qcom,initial-pwrlevel = <6>;
				qcom,ca-target-pwrlevel = <5>;

				/* TURBO_L1 */
				qcom,gpu-pwrlevel@0 {
					reg = <0>;
					qcom,gpu-freq = <980000000>;
					qcom,bus-freq = <11>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
					qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
				};

				/* TURBO */
				qcom,gpu-pwrlevel@1 {
					reg = <1>;
					qcom,gpu-freq = <900000000>;
					qcom,bus-freq = <11>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
					qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
				};

				/* NOM_L1 */
				qcom,gpu-pwrlevel@2 {
					reg = <2>;
					qcom,gpu-freq = <820000000>;
					qcom,bus-freq = <10>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
					qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
				};

				/* NOM */
				qcom,gpu-pwrlevel@3 {
					reg = <3>;
					qcom,gpu-freq = <745000000>;
					qcom,bus-freq = <9>;
					qcom,bus-min = <8>;
					qcom,bus-max = <10>;
					qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
				};

				/* SVS_L1 */
				qcom,gpu-pwrlevel@4 {
					reg = <4>;
					qcom,gpu-freq = <600000000>;
					qcom,bus-freq = <8>;
					qcom,bus-min = <8>;
					qcom,bus-max = <9>;
					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
				};

				/* SVS */
				qcom,gpu-pwrlevel@5 {
					reg = <5>;
					qcom,gpu-freq = <465000000>;
					qcom,bus-freq = <7>;
					qcom,bus-min = <5>;
					qcom,bus-max = <8>;
					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
				};

				/* LOW SVS */
				qcom,gpu-pwrlevel@6 {
					reg = <6>;
					qcom,gpu-freq = <320000000>;
					qcom,bus-freq = <4>;
					qcom,bus-min = <3>;
					qcom,bus-max = <5>;
					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};

				/* XO */
				qcom,gpu-pwrlevel@7 {
					reg = <7>;
					qcom,gpu-freq = <0>;
					qcom,bus-freq = <0>;
					qcom,bus-min = <0>;
					qcom,bus-max = <0>;
					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};
			};

			qcom,gpu-pwrlevels-2 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <200>;

				qcom,initial-pwrlevel = <6>;
				qcom,ca-target-pwrlevel = <5>;

				/* TURBO_L1 */
				qcom,gpu-pwrlevel@0 {
					reg = <0>;
					qcom,gpu-freq = <950000000>;
					qcom,bus-freq = <11>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
					qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
				};

				/* TURBO */
				qcom,gpu-pwrlevel@1 {
					reg = <1>;
					qcom,gpu-freq = <900000000>;
					qcom,bus-freq = <11>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
					qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
				};

				/* NOM_L1 */
				qcom,gpu-pwrlevel@2 {
					reg = <2>;
					qcom,gpu-freq = <820000000>;
					qcom,bus-freq = <10>;
					qcom,bus-min = <10>;
					qcom,bus-max = <11>;
					qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
				};

				/* NOM */
				qcom,gpu-pwrlevel@3 {
					reg = <3>;
					qcom,gpu-freq = <745000000>;
					qcom,bus-freq = <9>;
					qcom,bus-min = <8>;
					qcom,bus-max = <10>;
					qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
				};

				/* SVS_L1 */
				qcom,gpu-pwrlevel@4 {
					reg = <4>;
					qcom,gpu-freq = <600000000>;
					qcom,bus-freq = <8>;
					qcom,bus-min = <8>;
					qcom,bus-max = <9>;
					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
				};

				/* SVS */
				qcom,gpu-pwrlevel@5 {
					reg = <5>;
					qcom,gpu-freq = <465000000>;
					qcom,bus-freq = <7>;
					qcom,bus-min = <5>;
					qcom,bus-max = <8>;
					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
				};

				/* LOW SVS */
				qcom,gpu-pwrlevel@6 {
					reg = <6>;
					qcom,gpu-freq = <320000000>;
					qcom,bus-freq = <4>;
					qcom,bus-min = <3>;
					qcom,bus-max = <5>;
					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};

				/* XO */
				qcom,gpu-pwrlevel@7 {
					reg = <7>;
					qcom,gpu-freq = <0>;
					qcom,bus-freq = <0>;
					qcom,bus-min = <0>;
					qcom,bus-max = <0>;
					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};
			};

			qcom,gpu-pwrlevels-3 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <157>;

				qcom,initial-pwrlevel = <3>;
				qcom,ca-target-pwrlevel = <2>;

				/* NOM */
				qcom,gpu-pwrlevel@0 {
					reg = <0>;
					qcom,gpu-freq = <745000000>;
					qcom,bus-freq = <11>;
					qcom,bus-min = <9>;
					qcom,bus-max = <11>;
					qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
				};

				/* SVS_L1 */
				qcom,gpu-pwrlevel@1 {
					reg = <1>;
					qcom,gpu-freq = <600000000>;
					qcom,bus-freq = <8>;
					qcom,bus-min = <8>;
					qcom,bus-max = <10>;
					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
				};

				/* SVS */
				qcom,gpu-pwrlevel@2 {
					reg = <2>;
					qcom,gpu-freq = <465000000>;
					qcom,bus-freq = <7>;
					qcom,bus-min = <5>;
					qcom,bus-max = <8>;
					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
				};

				/* LOW SVS */
				qcom,gpu-pwrlevel@3 {
					reg = <3>;
					qcom,gpu-freq = <320000000>;
					qcom,bus-freq = <4>;
					qcom,bus-min = <3>;
					qcom,bus-max = <5>;
					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};

				/* XO */
				qcom,gpu-pwrlevel@4 {
					reg = <4>;
					qcom,gpu-freq = <0>;
					qcom,bus-freq = <0>;
					qcom,bus-min = <0>;
					qcom,bus-max = <0>;
					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};
			};

			qcom,gpu-pwrlevels-4 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <127>;

				qcom,initial-pwrlevel = <2>;
				qcom,ca-target-pwrlevel = <1>;

				/* SVS_L1 */
				qcom,gpu-pwrlevel@0 {
					reg = <0>;
					qcom,gpu-freq = <600000000>;
					qcom,bus-freq = <11>;
					qcom,bus-min = <8>;
					qcom,bus-max = <11>;
					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
				};

				/* SVS */
				qcom,gpu-pwrlevel@1 {
					reg = <1>;
					qcom,gpu-freq = <465000000>;
					qcom,bus-freq = <7>;
					qcom,bus-min = <5>;
					qcom,bus-max = <9>;
					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
				};

				/* LOW SVS */
				qcom,gpu-pwrlevel@2 {
					reg = <2>;
					qcom,gpu-freq = <320000000>;
					qcom,bus-freq = <4>;
					qcom,bus-min = <3>;
					qcom,bus-max = <5>;
					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};

				/* XO */
				qcom,gpu-pwrlevel@3 {
					reg = <3>;
					qcom,gpu-freq = <0>;
					qcom,bus-freq = <0>;
					qcom,bus-min = <0>;
					qcom,bus-max = <0>;
					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};
			};

		};
};


&soc {
	gpu_opp_table: gpu-opp-table {
		compatible = "operating-points-v2";

		opp-980000000 {
			opp-hz = /bits/ 64 <980000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
		};

		opp-950000000 {
			opp-hz = /bits/ 64 <950000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
		};

		opp-900000000 {
			opp-hz = /bits/ 64 <900000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
		};

		opp-820000000 {
			opp-hz = /bits/ 64 <820000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
		};

		opp-745000000 {
			opp-hz = /bits/ 64 <745000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
		};

		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
		};

		opp-465000000 {
			opp-hz = /bits/ 64 <465000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
		};

		opp-320000000 {
			opp-hz = /bits/ 64 <320000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
		};
	};

	gpu_bw_tbl: gpu-bw-tbl {
		compatible = "operating-points-v2";

		opp-0    { opp-hz = /bits/ 64 < 0 >;     }; /*  OFF */

		opp-100  { opp-hz = /bits/ 64 < 762 >;   }; /*  1.100 MHz */

		opp-200  { opp-hz = /bits/ 64 < 1525 >;  }; /*  2.200 MHz */

		opp-300  { opp-hz = /bits/ 64 < 2288 >;  }; /*  3.300 MHz */

		opp-451  { opp-hz = /bits/ 64 < 3440 >;  }; /*  4.451 MHz */

		opp-547  { opp-hz = /bits/ 64 < 4173 >;  }; /*  5.547 MHz */

		opp-681  { opp-hz = /bits/ 64 < 5195 >;  }; /*  6.681 MHz */

		opp-768  { opp-hz = /bits/ 64 < 5859 >;  }; /*  7.768 MHz */

		opp-1017 { opp-hz = /bits/ 64 < 7759 >;  }; /*  8.1017 MHz */

		opp-1353 { opp-hz = /bits/ 64 < 10322 >; }; /*  9.1353 MHz */

		opp-1555 { opp-hz = /bits/ 64 < 11863 >; }; /* 10.1555 MHz */

		opp-1804 { opp-hz = /bits/ 64 < 13763 >; }; /* 11.1804 MHz */
	};

	gpubw: qcom,gpubw {
		compatible = "qcom,devbw";
		governor = "bw_vbif";
		qcom,src-dst-ports = <26 512>;
		operating-points-v2 = <&gpu_bw_tbl>;
	};

	kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 {
		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x59a0000 0x10000>;
		qcom,protect = <0xa0000 0x10000>;

		vddcx-supply = <&gpu_cx_gdsc>;
		qcom,retention;
		qcom,hyp_secure_alloc;

		gfx3d_user: gfx3d_user {
			compatible = "qcom,smmu-kgsl-cb";
			label = "gfx3d_user";
			iommus = <&kgsl_smmu 0 1>;
			qcom,iommu-dma = "disabled";
			qcom,gpu-offset = <0xa8000>;
		};

		gfx3d_secure: gfx3d_secure {
			compatible = "qcom,smmu-kgsl-cb";
			label = "gfx3d_secure";
			iommus = <&kgsl_smmu 2 0>;
			qcom,iommu-dma = "disabled";
		};
	};
};