#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/clock/qcom,apsscc-sdxlemur.h>
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,qcs405.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>

#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}

/ {
	model = "Qualcomm Technologies, Inc. QCS405";
	compatible = "qcom,qcs405";
	qcom,msm-id = <352 0x0>, <452 0x0>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		bootargs = "console=ttyMSM0,115200n8 earlycon=msm_serial_dm,0x78b1000 loglevel=6 kpti=0 log_buf_len=256K kernel.panic_on_rcu_stall=1 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops fw_devlink.strict=1 cpufreq.default_governor=performance printk.console_no_auto_verbose=1 kasan=off cgroup.memory=nokmem,nosocket";
	};

	memory { device_type = "memory"; reg = <0 0 0 0>; };

	firmware: firmware {
	};

	reserved_mem: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		removed_region0: removed_region@85900000 {
			no-map;
			reg = <0x0 0x85900000 0x0 0x600000>;
		};

		smem_region: smem@85f00000 {
			no-map;
			reg = <0x0 0x85f00000 0x0 0x200000>;
		};

		removed_region1: removed_region@86100000 {
			no-map;
			reg = <0x0 0x86100000 0x0 0x300000>;
		};

		wlan_fw_mem: wlan_fw_mem@86400000 {
			no-map;
			reg = <0x0 0x86400000 0x0 0x1000000>;
		};

		adsp_fw_mem: adsp_fw_mem@87400000 {
			no-map;
			reg = <0x0 0x87400000 0x0 0x1400000>;
		};

		cdsp_fw_mem: cdsp_fw_mem@88800000 {
			no-map;
			reg = <0x0 0x88800000 0x0 0x800000>;
		};

		wlan_msa_mem: wlan_msa_region@89000000 {
			no-map;
			reg = <0x0 0x89000000 0x0 0x100000>;
		};

		mdf_mem: mdf_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x800000>;
		};

		qseecom_mem: qseecom_region {
			compatible = "shared-dma-pool";
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x1000000>;
		};

		qseecom_ta_mem: qseecom_ta_region {
			compatible = "shared-dma-pool";
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x400000>;
		};

		adsp_mem: adsp_region {
			compatible = "shared-dma-pool";
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x800000>;
		};

		dump_mem: mem_dump_region {
			compatible = "shared-dma-pool";
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x400000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x1000000>;
			linux,cma-default;
		};
	};

	aliases: aliases {
		serial0 = &blsp1_uart2_console;
		mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
		mmc1 = &sdhc_2; /*SDC2 SD Card slot*/
	};

	soc: soc { };

};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@b000000 {
		compatible = "qcom,msm-qgic2";
		interrupt-controller;
		interrupt-parent = <&intc>;
		#interrupt-cells = <3>;
		reg = <0x0b000000 0x1000>,
		      <0x0b002000 0x1000>;
	};

	mpm: interrupt-controller@601b8 {
		compatible = "qcom,mpm-qcs405", "qcom,mpm";
		interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
		reg = <0x601b8 0x1000>,
		      <0xb011008 0x4>,  /* MSM_APCS_GCC_BASE 4K */
		      <0xb121000 0x1000>;
		reg-names = "vmpm", "ipc", "timer";
		qcom,num-mpm-irqs = <96>;
		interrupt-controller;
		interrupt-parent = <&intc>;
		#interrupt-cells = <2>;
	};

	qcom,spm@b012000 {
		compatible = "qcom,spm-v2";
		reg = <0xb012000 0x1000>;
		qcom,name = "perf-l2";
		qcom,saw2-ver-reg = <0xfd0>;
		qcom,saw2-cfg = <0x14>;
		qcom,saw2-spm-dly= <0x3C11840A>;
		qcom,saw2-spm-ctl = <0xe>;
		qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>;
		qcom,vctl-timeout-us = <500>;
		qcom,vctl-port = <0x0>;
		qcom,vctl-port-ub = <0x1>;
		qcom,pfm-port = <0x02>;
	};

	qcom-secure-buffer {
		compatible = "qcom,secure-buffer";
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	memtimer@b120000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0xb120000 0x1000>;
		clock-frequency = <19200000>;
		frame@b121000 {
			frame-number = <0>;
			interrupts = <0 8 0x4>,
				     <0 7 0x4>;
			reg = <0xb121000 0x1000>,
			      <0xb122000 0x1000>;
		};

		frame@b123000 {
			frame-number = <1>;
			interrupts = <0 9 0x4>;
			reg = <0xb123000 0x1000>;
			status = "disabled";
		};

		frame@b124000 {
			frame-number = <2>;
			interrupts = <0 10 0x4>;
			reg = <0xb124000 0x1000>;
			status = "disabled";
		};

		frame@b125000 {
			frame-number = <3>;
			interrupts = <0 11 0x4>;
			reg = <0xb125000 0x1000>;
			status = "disabled";
		};

		frame@b126000 {
			frame-number = <4>;
			interrupts = <0 12 0x4>;
			reg = <0xb126000 0x1000>;
			status = "disabled";
		};

		frame@b127000 {
			frame-number = <5>;
			interrupts = <0 13 0x4>;
			reg = <0xb127000 0x1000>;
			status = "disabled";
		};

		frame@b128000 {
			frame-number = <6>;
			interrupts = <0 14 0x4>;
			reg = <0xb128000 0x1000>;
			status = "disabled";
		};
	};

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			clock-frequency = <19200000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		pcie_0_pipe_clk: pcie_0_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_0_pipe_clk";
			#clock-cells = <0>;
		};
	};

	rpmcc: qcom,rpmcc {
		compatible = "qcom,rpmcc-qcs404";
		#clock-cells = <1>;
	};

	gcc: clock-controller@1800000 {
		compatible = "qcom,gcc-qcs404", "syscon";
		reg = <0x1800000 0x80000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_sr_pll-supply = <&VDD_SR_PLL_LEVEL>;
		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&pcie_0_pipe_clk>,
			 <&rpmcc RPM_SMD_XO_A_CLK_SRC>;
		clock-names = "bi_tcxo", "pcie_0_pipe_clk", "bi_tcxo_ao";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	cmn_blk_pll: qcom,cmn_blk_pll@2f780 {
		compatible = "qcom,cmn_blk_pll";
		reg = <0x2f780 0x4>;
		reg-names = "cmn_blk";
		clocks = <&gcc GCC_BIAS_PLL_MISC_RESET_CLK>,
			 <&gcc GCC_BIAS_PLL_AHB_CLK>,
			 <&gcc GCC_BIAS_PLL_AON_CLK>,
			 <&rpmcc RPM_SMD_XO_CLK_SRC>;
		clock-names = "misc_reset_clk",
			      "ahb_clk",
			      "aon_clk",
			      "bi_tcxo";
		resets = <&gcc GCC_BIAS_PLL_BCR>;
		reset-names = "cmn_blk_pll_reset";
		#clock-cells = <1>;
	};

	cpucc: syscon@b01101c {
		compatible = "syscon";
		reg = <0xb01101c 0x4>;
	};

	debugcc: debug-clock-controller@0 {
		compatible = "qcom,qcs404-debugcc";
		qcom,gcc = <&gcc>;
		qcom,cpucc = <&cpucc>;
		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
		clock-names = "xo_clk_src";
		#clock-cells = <1>;
	};

	apsscc: clock-controller@0b011050 {
		compatible = "qcom,qcs404-apsscc";
		clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
			<&gcc GCC_GPLL0_AO_OUT_MAIN>;
		clock-names = "bi_tcxo_ao", "gpll0_out_even";
		reg = <0xb011050 0x16>, <0xb016000 0x34>;
		reg-names = "apcs_cmd" , "apcs_pll";
		cpu-vdd-supply = <&apc_vreg_corner>;
		vdd_dig_ao-supply = <&pms405_s1_level_ao>;
		vdd_hf_pll-supply = <&pms405_l5_ao>;
		qcom,speed0-bin-v0 =
			< 0         0>,
			< 1094400000 1>,
			< 1248000000 2>,
			< 1401600000 3>;
		#clock-cells = <1>;
	};

	/* GDSCs in Global CC */
	gdsc_mdss: qcom,gdsc@184d078 {
		compatible = "qcom,gdsc";
		regulator-name = "gdsc_mdss";
		reg = <0x184d078 0x4>;
	};

	gdsc_oxili_gx: qcom,gdsc@185901c {
		compatible = "qcom,gdsc";
		regulator-name = "gdsc_oxili_gx";
		reg = <0x185901c 0x4>;
	};

	restart@4ab000 {
		compatible = "qcom,pshold";
		reg = <0x4ab000 0x4>,
			<0x193d100 0x4>;
		reg-names = "pshold-base", "tcsr-boot-misc-detect";
	};

	qcom,sps {
		compatible = "qcom,msm-sps-4k";
		qcom,pipe-attr-ee;
	};

	qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>;
	};

	qcom,mpm2-sleep-counter@4a3000 {
		compatible = "qcom,mpm2-sleep-counter";
		reg = <0x4a3000 0x1000>;
		clock-frequency = <32768>;
	};

	cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	qcom,msm-imem@8600000 {
		compatible = "qcom,msm-imem";
		reg = <0x08600000 0x1000>; /* Address and size of IMEM */
		ranges = <0x0 0x08600000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 0x8>;
		};

		dload_type@18 {
			compatible = "qcom,msm-imem-dload-type";
			reg = <0x18 0x4>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 0x4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 0x20>;
		};

		pil@94c {
			compatible = "qcom,pil-reloc-info";
			reg = <0x94c 0xc8>;
		};

		pil@6dc {
			compatible = "qcom,msm-imem-pil-disable-timeout";
			reg = <0x6dc 0x4>;
		};

		diag_dload@c8 {
			compatible = "qcom,msm-imem-diag-dload";
			reg = <0xc8 0xc8>;
		};

		kaslr_offset@6d0 {
			compatible = "qcom,msm-imem-kaslr_offset";
			reg = <0x6d0 0xc>;
		};

	};

	mini_dump_mode {
		compatible = "qcom,minidump";
		status = "ok";
	};

	vendor_hooks: qcom,cpu-vendor-hooks {
		compatible = "qcom,cpu-vendor-hooks";
	};

	spmi_bus: qcom,spmi@200f000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0x200f000 0x1000>,
			<0x2400000 0x800000>,
			<0x2c00000 0x800000>,
			<0x3800000 0x200000>,
			<0x200a000 0x2100>;
		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
		interrupt-names = "periph_irq";
		interrupts-extended = <&mpm 62 IRQ_TYPE_LEVEL_HIGH>;
		qcom,ee = <0>;
		qcom,channel = <0>;
		#address-cells = <2>;
		#size-cells = <0>;
		interrupt-controller;
		#interrupt-cells = <4>;
		cell-index = <0>;
	};

	wdog: qcom,wdt@b017000 {
		compatible = "qcom,msm-watchdog";
		reg = <0xb017000 0x1000>;
		reg-names = "wdt-base";
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bark-time = <11000>;
		qcom,pet-time = <9744>;
		qcom,ipi-ping;
		qcom,wakeup-enable;
		status = "okay";
	};

	dcc: dcc_v2@b2000 {
		compatible = "qcom,dcc-v2";
		reg = <0x000b2000 0x1000>,
		      <0x000bfc00 0x400>;

		reg-names = "dcc-base", "dcc-ram-base";
		dcc-ram-offset = <0x400>;
		qcom,curr-link-list = <1>;
	};

	rpm_bus: qcom,rpm-smd {
		compatible = "qcom,rpm-smd";
		rpm-channel-name = "rpm_requests";
		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
		rpm-channel-type = <15>; /* SMD_APPS_RPM */
		power-domains = <&CLUSTER_PD>;
	};

	cluster-device {
		compatible = "qcom,lpm-cluster-dev";
		power-domains = <&CLUSTER_PD>;
	};

	rpm-sleep-stats@290000 {
		compatible = "qcom,rpm-sleep-stats";
		reg = <0x290000 0x1000>;
	};

	qcom,rpm-master-stats@60150 {
		compatible = "qcom,rpm-master-stats";
		reg = <0x60150 0x5000>;
		qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ";
		qcom,master-stats-version = <2>;
		qcom,master-offset = <4096>;
	};

	mem_dump {
		compatible = "qcom,mem-dump";
		memory-region = <&dump_mem>;

		rpm_sw_dump {
			qcom,dump-size = <0x28000>;
			qcom,dump-id = <0xea>;
		};

		pmic_dump {
			qcom,dump-size = <0x10000>;
			qcom,dump-id = <0xe4>;
		};

		misc_data_dump {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0xe8>;
		};

		vsense_dump {
			qcom,dump-size = <0x10000>;
			qcom,dump-id = <0xe9>;
		};

		tmc_etf_dump {
			qcom,dump-size = <0x10000>;
			qcom,dump-id = <0xf0>;
		};

		tmc_etr_reg_dump {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x100>;
		};

		tmc_etf_reg_dump {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x101>;
		};

		c0_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x0>;
		};

		c1_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x1>;
		};

		c2_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x2>;
		};

		c3_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x3>;
		};

		l2_dump1 {
			qcom,dump-size = <0x0>;
			qcom,dump-id = <0xC1>;
		};

		l1_i_cache100 {
			qcom,dump-size = <0x8800>;
			qcom,dump-id = <0x60>;
		};

		l1_i_cache101 {
			qcom,dump-size = <0x8800>;
			qcom,dump-id = <0x61>;
		};

		l1_i_cache102 {
			qcom,dump-size = <0x8800>;
			qcom,dump-id = <0x62>;
		};

		l1_i_cache103 {
			qcom,dump-size = <0x8800>;
			qcom,dump-id = <0x63>;
		};

		l1_d_cache100 {
			qcom,dump-size = <0x9000>;
			qcom,dump-id = <0x80>;
		};

		l1_d_cache101 {
			qcom,dump-size = <0x9000>;
			qcom,dump-id = <0x81>;
		};

		l1_d_cache102 {
			qcom,dump-size = <0x9000>;
			qcom,dump-id = <0x82>;
		};

		l1_d_cache103 {
			qcom,dump-size = <0x9000>;
			qcom,dump-id = <0x83>;
		};
	};

	remoteproc_cdsp: remoteproc-cdsp@800000 {
		compatible = "qcom,qcs405-cdsp-pas";
		reg = <0x800000 0x00100>;

		vdd_cx-supply = <&pms405_s1_level>;
		reg-names = "vdd_cx";

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
		clock-names = "xo";

		vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;

		/* GPIO inputs from turning */
		interrupts-extended = <&intc 0 229 1>,
				<&cdsp_smp2p_in 0 0>,
				<&cdsp_smp2p_in 2 0>,
				<&cdsp_smp2p_in 1 0>,
				<&cdsp_smp2p_in 3 0>,
				<&cdsp_smp2p_in 7 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack",
				"shutdown-ack";

		/* GPIO output to turning */
		qcom,smem-states = <&cdsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";
		memory-region = <&cdsp_fw_mem>;
		glink-edge {
			qcom,remote-pid = <5>;
			transport = "smem";
			mboxes = <&apcs_glb 12>;
			mbox-names = "cdsp_smem";
			interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;

			label = "cdsp";
			qcom,glink-label = "cdsp";

			qcom,cdsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};
		};
	};

	wlan_dsp:remoteproc-wpss@7000000 {
		compatible = "qcom,qcs405-wlan-dsp";
		reg = <0x07000000 0x580000>;

		vdd_cx-supply = <&pms405_s1_level>;
		reg-names = "vdd_cx";
		vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
		clock-names = "xo";

		/* GPIO inputs from wcnss */
		interrupts-extended =  <&intc 0 153 1>,
				<&modem_smp2p_in 0 0>,
				<&modem_smp2p_in 2 0>,
				<&modem_smp2p_in 1 0>,
				<&modem_smp2p_in 3 0>,
				<&modem_smp2p_in 7 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack",
				"shutdown-ack";

		/* GPIO output to wcnss */
		qcom,smem-states = <&modem_smp2p_out 0>;
		qcom,smem-state-names = "stop";
		memory-region = <&wlan_fw_mem>;
		glink-edge {
			qcom,remote-pid = <1>;
			transport = "smem";
			mboxes = <&apcs_glb 16>;
			mbox-names = "wcnss_smem";
			interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;

			label = "wcnss";
			qcom,glink-label = "mpss";

			qcom,wcnss_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};
		};
	};

	adsp_pas:remoteproc-adsp@c000000 {
		compatible = "qcom,qcs405-adsp-pas";
		reg = <0xc000000 0x00100>;

		vdd_cx-supply = <&pms405_s2_level>;
		reg-names = "vdd_cx";
		vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
		clock-names = "xo";

		memory-region = <&adsp_fw_mem>;

		/* Inputs from lpass */
		interrupts-extended = <&intc 0 293 1>,
				      <&adsp_smp2p_in 0 0>,
				      <&adsp_smp2p_in 2 0>,
				      <&adsp_smp2p_in 1 0>,
				      <&adsp_smp2p_in 3 0>,
				      <&adsp_smp2p_in 7 0>;

		interrupt-names = "wdog",
				  "fatal",
				  "handover",
				  "ready",
				  "stop-ack",
				  "shutdown-ack";
		/* GPIO output to lpass */
		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";
		glink_edge: glink-edge {
			qcom,remote-pid = <2>;
			transport = "smem";
			mboxes = <&apcs_glb 8>;
			mbox-names = "adsp_smem";
			interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;

			label = "adsp";
			qcom,glink-label = "lpass";

			qcom,adsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,low-latency;
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
				qcom,non-wake-svc = <0x51
						0x190>;
			};

			qcom,apr_tal_rpmsg {
				qcom,glink-channels = "apr_audio_svc";
				qcom,intents = <0x200 20>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};
		};
	};

	qcom,glinkpkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-at-mdm0 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DS";
			qcom,glinkpkt-dev-name = "at_mdm0";
		};

		qcom,glinkpkt-apr-apps2 {
			qcom,glinkpkt-edge = "adsp";
			qcom,glinkpkt-ch-name = "apr_apps2";
			qcom,glinkpkt-dev-name = "apr_apps2";
		};

		qcom,glinkpkt-data40-cntl {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA40_CNTL";
			qcom,glinkpkt-dev-name = "smdcntl8";
		};

		qcom,glinkpkt-data1 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA1";
			qcom,glinkpkt-dev-name = "smd7";
		};

		qcom,glinkpkt-data4 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA4";
			qcom,glinkpkt-dev-name = "smd8";
		};

		qcom,glinkpkt-data11 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA11";
			qcom,glinkpkt-dev-name = "smd11";
		};
	};

	tcsr_mutex_block: syscon@1905000 {
		compatible = "syscon";
		reg = <0x1905000 0x20000>;
	};

	tcsr: syscon@1937000 {
		compatible = "syscon";
		reg = <0x1937000 0x30000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem: qcom,smem {
		compatible = "qcom,smem";
		memory-region = <&smem_region>;
		hwlocks = <&tcsr_mutex 3>;
	};

	rpm_msg_ram: memory@60000 {
		compatible = "qcom,rpm-msg-ram";
		reg = <0x60000 0x6000>;
	};

	apcs: syscon@b011008 {
		compatible = "syscon";
		reg = <0xb011008 0x4>;
	};

	apcs_glb: mailbox@b011000 {
		compatible = "qcom,msm8916-apcs-kpss-global";
		reg = <0xb011000 0x10>;

		#mbox-cells = <1>;
	};

	rpm-glink {
		compatible = "qcom,glink-rpm";
		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;
		mboxes = <&apcs_glb 0>;
	};

	qcom,glink {
		compatible = "qcom,glink";
	};

	qcom,smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 18>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 10>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sleepstate_smp2p_out: sleepstate-out {
			qcom,entry-name = "sleepstate";
			#qcom,smem-state-cells = <1>;
		};

		sleepstate_smp2p_in: qcom,sleepstate-in {
			qcom,entry-name = "sleepstate_see";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p_sleepstate: qcom,smp2p_sleepstate {
		compatible = "qcom,smp2p-sleepstate";
		qcom,smem-states = <&sleepstate_smp2p_out 0>;
		interrupt-parent = <&sleepstate_smp2p_in>;
		interrupts = <0 0>;
		interrupt-names = "smp2p-sleepstate-in";
	};

	qcom,msm-adsprpc-mem {
		compatible = "qcom,msm-adsprpc-mem-region";
		memory-region = <&adsp_mem>;
	};

	qcom,msm_fastrpc {
		compatible = "qcom,msm-fastrpc-compute";
		qcom,adsp-remoteheap-vmid = <22 37>;
		qcom,rpc-latency-us = <611>;
		qcom,fastrpc-adsp-audio-pdr;
		qcom,fastrpc-adsp-sensors-pdr;
		qcom,fastrpc-gids = <2908>;
		qcom,fastrpc-legacy-remote-heap;

		qcom,msm_fastrpc_compute_cb1 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1001 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
		};

		qcom,msm_fastrpc_compute_cb2 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1002 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
		};

		qcom,msm_fastrpc_compute_cb3 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1003 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
		};

		qcom,msm_fastrpc_compute_cb4 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1004 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
		};

		qcom,msm_fastrpc_compute_cb5 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1005 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
		};

		qcom,msm_fastrpc_compute_cb6 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x804 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
		};

		qcom,msm_fastrpc_compute_cb7 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x805 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
		};

		qcom,msm_fastrpc_compute_cb8 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x806 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			shared-cb = <5>;
		};
	};

	qcom,msm-cdsp-loader {
		compatible = "qcom,cdsp-loader";
		qcom,proc-img-to-load = "cdsp";
		qcom,rproc-handle = <&remoteproc_cdsp>;
	};

	qcom,smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom_crypto: qcrypto@720000 {
		compatible = "qcom,qcrypto";
		reg = <0x720000 0x20000>,
			<0x704000 0x20000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bam-pipe-pair = <2>;
		qcom,ce-hw-instance = <0>;
		qcom,ce-device = <0>;
		qcom,bam-ee = <0>;
		qcom,ce-hw-shared;
		qcom,clk-mgmt-sus-res;
		interconnect-names = "data_path";
		interconnects = <&pc_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
		clock-names =
			"core_clk_src", "core_clk",
			"iface_clk", "bus_clk";
		clocks =
			<&rpmcc RPM_SMD_CE1_CLK>,
			<&rpmcc RPM_SMD_CE1_CLK>,
			<&rpmcc RPM_SMD_CE1_CLK>,
			<&rpmcc RPM_SMD_CE1_CLK>;
		qcom,use-sw-aes-cbc-ecb-ctr-algo;
		qcom,use-sw-aes-xts-algo;
		qcom,use-sw-aes-ccm-algo;
		qcom,use-sw-ahash-algo;
		qcom,use-sw-hmac-algo;
		qcom,use-sw-aead-algo;
		qcom,smmu-s1-enable;
		iommus = <&apps_smmu 0x0064 0x0011>,
			<&apps_smmu 0x0074 0x0011>;
	};

	qcom_cedev: qcedev@720000 {
		compatible = "qcom,qcedev";
		reg = <0x720000 0x20000>,
			<0x704000 0x20000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <0 206 0>;
		qcom,ce-device = <0>;
		qcom,bam-ee = <0>;
		qcom,ce-hw-shared;
		qcom,clk-mgmt-sus-res;
		qcom,bam-pipe-pair = <3>;
		qcom,ce-hw-instance = <0>;
		interconnect-names = "data_path";
		interconnects = <&pc_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
		clock-names =
			"core_clk_src", "core_clk",
			"iface_clk", "bus_clk";
		clocks =
			<&rpmcc RPM_SMD_CE1_CLK>,
			<&rpmcc RPM_SMD_CE1_CLK>,
			<&rpmcc RPM_SMD_CE1_CLK>,
			<&rpmcc RPM_SMD_CE1_CLK>;
		qcom,smmu-s1-enable;
		iommus = <&apps_smmu 0x0066 0x0011>,
			<&apps_smmu 0x0076 0x0011>;
		qcom_cedev_ns_cb {
			compatible = "qcom,qcedev,context-bank";
			label = "ns_context";
			iommus = <&apps_smmu 0x0066 0>,
				<&apps_smmu 0x0076 0>;
		};
	};

	qcom_rng: qrng@e3000 {
		compatible = "qcom,msm-rng";
		reg = <0xe3000 0x1000>;
		qcom,msm-rng-iface-clk;
		qcom,no-qrng-config;
		interconnect-names = "data_path";
		interconnects = <&bimc MASTER_AMPSS_M0 &pc_noc SLAVE_PRNG>;
		clocks = <&gcc GCC_PRNG_AHB_CLK>;
		clock-names = "km_clk_src";
	};

	qcom_tzlog: tz-log@8600720 {
		compatible = "qcom,tz-log";
		reg = <0x08600720 0x2000>;
	};

	thermal_zones: thermal-zones {};

	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
		qcom,disable-shmbridge-support;
	};

	qcom_qseecom: qseecom@85900000 {
		compatible = "qcom,qseecom";
		reg = <0x85900000 0x500000>;
		reg-names = "secapp-region";
		memory-region = <&qseecom_mem>;
		qseecom_mem = <&qseecom_mem>;
		qseecom_ta_mem = <&qseecom_ta_mem>;
		qcom,hlos-num-ce-hw-instances = <1>;
		qcom,hlos-ce-hw-instance = <0>;
		qcom,qsee-ce-hw-instance = <0>;
		qcom,disk-encrypt-pipe-pair = <2>;
		qcom,support-fde;
		qcom,fde-key-size;
		qcom,no-clock-support;
		qcom,appsbl-qseecom-support;
		qcom,ce-opp-freq = <171430000>;
		qcom,qsee-reentrancy-support = <2>;
	};

	bimc: interconnect@400000 {
		reg = <0x400000 0x80000>;
		compatible = "qcom,qcs405-bimc";
		qcom,util-factor = <153>;
		qcom,keepalive;
		#interconnect-cells = <1>;
		clock-names = "bus", "bus_a";
		clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
			<&rpmcc RPM_SMD_BIMC_A_CLK>;
	};

	pc_noc: interconnect@500000 {
		reg = <0x500000 0x15080>;
		compatible = "qcom,qcs405-pcnoc";
		qcom,keepalive;
		#interconnect-cells = <1>;
		clock-names = "bus", "bus_a";
		clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
			<&rpmcc RPM_SMD_PNOC_A_CLK>;
	};

	system_noc: interconnect@580000 {
		reg = <0x580000 0x23080>;
		compatible = "qcom,qcs405-snoc";
		qcom,keepalive;
		#interconnect-cells = <1>;
		clock-names = "bus", "bus_a";
		clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
			<&rpmcc RPM_SMD_SNOC_A_CLK>,
			<&gcc GCC_SYS_NOC_USB3_CLK>;
	};

	sdhc1_opp_table: sdhc1-opp-table {
		compatible = "operating-points-v2";

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			opp-peak-kBps = <500000 200000>;
			opp-avg-kBps = <104000 0>;
		};

		opp-384000000 {
			opp-hz = /bits/ 64 <384000000>;
			opp-peak-kBps = <2500000 1000000>;
			opp-avg-kBps = <400000 0>;
		};
	};

	sdhc2_opp_table: sdhc2-opp-table {
		compatible = "operating-points-v2";

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			opp-peak-kBps = <1600000 280000>;
			opp-avg-kBps = <50000 0>;
		};

		opp-202000000 {
			opp-hz = /bits/ 64 <202000000>;
			opp-peak-kBps = <5600000 1500000>;
			opp-avg-kBps = <104000 0>;
		};
	};

	sdhc_1: sdhci@7804000 {
		status = "ok";
		compatible = "qcom,sdhci-msm-v5";
		reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
		reg-names = "hc", "cqhci";

		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		clocks = <&gcc GCC_SDCC1_APPS_CLK>,
			<&gcc GCC_SDCC1_AHB_CLK>,
			<&gcc GCC_SDCC1_ICE_CORE_CLK>;
		clock-names = "core", "iface", "ice_core";

		qcom,ice-clk-rates = <300000000 100000000>;

		operating-points-v2 = <&sdhc1_opp_table>;

		interconnects = <&pc_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>,
			<&bimc MASTER_AMPSS_M0 &pc_noc SLAVE_SDCC_1>;
		interconnect-names = "sdhc-ddr","cpu-sdhc";

		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x000F6400 0x0 0x01 0x2c010800 0x80240874>;

		qcom,restore-after-cx-collapse;

		mmc-ddr-1_8v;
		mmc-hs200-1_8v;
		mmc-hs400-1_8v;
		mmc-hs400-enhanced-strobe;

		no-sd;
		no-sdio;

		bus-width = <8>;
		non-removable;
		supports-cqe;

		cap-mmc-hw-reset;

		/* VDD external regulator is enabled/disabled by pms405_l6 */
		vdd-supply = <&pms405_l6>;
		qcom,vdd-always-on;
		qcom,vdd-lpm-sup;
		qcom,vdd-voltage-level = <1800000 1800000>;
		qcom,vdd-current-level = <0 325000>;

		vdd-io-supply = <&pms405_l6>;
		qcom,vdd-io-always-on;
		qcom,vdd-io-lpm-sup;
		qcom,vdd-io-voltage-level = <1800000 1800000>;
		qcom,vdd-io-current-level = <0 325000>;

		pinctrl-names = "active", "sleep";
		pinctrl-0 = <&sdc1_on>;
		pinctrl-1 = <&sdc1_off>;

		qos0 {
			mask = <0x0f>;
			vote = <135>;
		};
	};

	sdhc_2: sdhci@7844000 {
		status = "disabled";
		compatible = "qcom,sdhci-msm-v5";
		reg = <0x7844000 0x1000>;
		reg-names = "hc";

		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
			<&gcc GCC_SDCC2_APPS_CLK>;
		clock-names = "iface", "core";

		operating-points-v2 = <&sdhc2_opp_table>;

		bus-width = <4>;
		no-sdio;
		no-mmc;
		qcom,restore-after-cx-collapse;

		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x000F6400 0x0 0x01 0x2c010800 0x00040874>;

		interconnects = <&pc_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>,
			<&bimc MASTER_AMPSS_M0 &pc_noc SLAVE_SDCC_2>;
		interconnect-names = "sdhc-ddr","cpu-sdhc";


		/* VDD is an external regulator eLDO5 */
		vdd-supply = <&pms405_l11>;
		qcom,vdd-voltage-level = <1800000 2950000>;
		qcom,vdd-current-level = <0 24200>;

		vdd-io-supply = <&pms405_l11>;
		qcom,vdd-io-voltage-level = <1800000 2950000>;
		qcom,vdd-io-current-level = <0 24200>;

		pinctrl-names = "active", "sleep";
		pinctrl-0 = <&sdc2_on>;
		pinctrl-1 = <&sdc2_off>;

		qos0 {
			mask = <0x0f>;
			vote = <651>;
		};
	};

	gpio_keys {
		compatible = "gpio-keys";
		label = "gpio-keys";
		input-name = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&tlmm_gpio_key_active>;

		vol_mute {
			label = "vol_mute";
			gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
			linux,input-type = <1>;
			linux,code = <KEY_MUTE>;
			debounce-interval = <15>;
			gpio-key,wakeup;
			linux,can-disable;
		};

		vol_down {
			label = "vol_down";
			gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
			linux,input-type = <1>;
			linux,code = <KEY_VOLUMEDOWN>;
			debounce-interval = <15>;
			gpio-key,wakeup;
			linux,can-disable;
		};

		vol_up {
			label = "vol_up";
			gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
			linux,input-type = <1>;
			linux,code = <KEY_VOLUMEUP>;
			debounce-interval = <15>;
			gpio-key,wakeup;
			linux,can-disable;
		};

		home {
			label = "action";
			gpios = <&tlmm 115 GPIO_ACTIVE_LOW>;
			linux,input-type = <1>;
			linux,code = <KEY_HOME>;
			debounce-interval = <15>;
			gpio-key,wakeup;
			linux,can-disable;
		};
	};

	slimbam_aud: bamdma@C184000 {
		compatible = "qcom,bam-v1.7.0";
		qcom,controlled-remotely;
		reg = <0xC184000 0x2A000>;
		reg-names = "bam";
		num-channels  = <31>;
		interrupts = <0 180 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		qcom,ee = <1>;
		qcom,num-ees = <2>;
	};

	slim_aud: slim@C1C0000 {
		compatible = "qcom,slim-ngd-v1.5.0";
		reg = <0xC1C0000 0x2C000>;
		reg-names = "ctrl";
		interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
		qcom,apps-ch-pipes = <0x0>;
		qcom,ea-pc = <0x2e0>;
		dmas = <&slimbam_aud 3>, <&slimbam_aud 4>;
		dma-names = "rx", "tx";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	slimbam_qca: bamdma@C204000 {
		compatible = "qcom,bam-v1.7.0";
		qcom,controlled-remotely;
		reg = <0xC204000 0x20000>;
		reg-names = "bam";
		num-channels  = <31>;
		interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		qcom,ee = <1>;
		qcom,num-ees = <2>;
	};

	slim_qca: slim@C240000 {
		compatible = "qcom,slim-ngd-v1.5.0";
		reg = <0xC240000 0x2C000>;
		reg-names = "ctrl";
		interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
		dmas = <&slimbam_qca 3>, <&slimbam_qca 4>;
		dma-names = "rx", "tx";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	msm_cpufreq: qcom,msm-cpufreq {
		compatible = "qcom,msm-cpufreq";
		clock-names = "cpu0_clk";
		clocks = <&apsscc APCS_MUX_CLK>;

		qcom,cpufreq-table =
			< 1094400 >,
			< 1248000 >,
			< 1401600 >;
	};

	mtl_rx_setup: rx-queues-config {
		snps,rx-queues-to-use = <4>;
		snps,rx-sched-sp;

		queue0 {
			snps,dcb-algorithm;
			snps,map-to-dma-channel = <0x0>;
			snps,route-up;
			snps,priority = <0x1>;
		};

		queue1 {
			snps,dcb-algorithm;
			snps,map-to-dma-channel = <0x1>;
			snps,route-ptp;
		};

		queue2 {
			snps,avb-algorithm;
			snps,map-to-dma-channel = <0x2>;
			snps,route-avcp;
		};

		queue3 {
			snps,avb-algorithm;
			snps,map-to-dma-channel = <0x3>;
			snps,priority = <0xC>;
		};
	};

	mtl_tx_setup: tx-queues-config {
		snps,tx-queues-to-use = <4>;
		snps,tx-sched-sp;
		queue0 {
			snps,dcb-algorithm;
		};

		queue1 {
			snps,dcb-algorithm;
		};

		queue2 {
			snps,avb-algorithm;
			snps,send_slope = <0x1000>;
			snps,idle_slope = <0x1000>;
			snps,high_credit = <0x3E800>;
			snps,low_credit = <0xFFC18000>;
		};

		queue3 {
			snps,avb-algorithm;
			snps,send_slope = <0x1000>;
			snps,idle_slope = <0x1000>;
			snps,high_credit = <0x3E800>;
			snps,low_credit = <0xFFC18000>;
		};
	};

	ethqos_hw: qcom,ethernet@07A80000 {
		compatible = "qcom,stmmac-ethqos","snps,dwmac-4.20a";
		reg = <0x07A80000 0x10000>,
			  <0x7A96000 0x100>;
		emac-phy-addr = <3>;
		reg-names = "stmmaceth", "rgmii", "tlmm-central-base";
		dma-bit-mask = <32>;
		emac-core-version = <0x20030000>;
		interrupts-extended = <&intc 0 56 4>, <&intc 0 55 4>,
			<&tlmm 61 2>, <&intc 0 300 4>, <&intc 0 301 4>;
		interrupt-names = "macirq", "eth_lpi",
			"phy-intr", "ptp_pps_irq_0", "ptp_pps_irq_1";
		snps,tso;
		snps,pbl = <32>;
		clocks = <&gcc GCC_ETH_AXI_CLK>,
			<&gcc GCC_ETH_SLAVE_AHB_CLK>,
			<&gcc GCC_ETH_PTP_CLK>,
			<&gcc GCC_ETH_RGMII_CLK>;
		clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
		snps,ptp-ref-clk-rate = <250000000>;
		snps,ptp-req-clk-rate = <57600000>;
		snps,reset-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
		qcom,phy-intr-redirect = <&tlmm 61 GPIO_ACTIVE_LOW>;
		/*gdsc_emac-supply = <&emac_gdsc>;*/
		rx-fifo-depth = <16384>;
		tx-fifo-depth = <20480>;
		snps,mtl-rx-config = <&mtl_rx_setup>;
		snps,mtl-tx-config = <&mtl_tx_setup>;

		pinctrl-names = "dev-emac-mdc", "dev-emac-mdio",
		"dev-emac-rgmii_txd0_state", "dev-emac-rgmii_txd1_state",
		"dev-emac-rgmii_txd2_state", "dev-emac-rgmii_txd3_state",
		"dev-emac-rgmii_txc_state",  "dev-emac-rgmii_tx_ctl_state",
		"dev-emac-rgmii_rxd0_state", "dev-emac-rgmii_rxd1_state",
		"dev-emac-rgmii_rxd2_state", "dev-emac-rgmii_rxd3_state",
		"dev-emac-rgmii_rxc_state", "dev-emac-rgmii_rx_ctl_state",
		"dev-emac-phy_intr", "dev-emac-phy_reset_state";

		pinctrl-0 = <&emac_mdc>;
		pinctrl-1 = <&emac_mdio>;
		pinctrl-2 = <&emac_rgmii_txd0>;
		pinctrl-3 = <&emac_rgmii_txd1>;
		pinctrl-4 = <&emac_rgmii_txd2>;
		pinctrl-5 = <&emac_rgmii_txd3>;
		pinctrl-6 = <&emac_rgmii_txc>;
		pinctrl-7 = <&emac_rgmii_tx_ctl>;
		pinctrl-8 = <&emac_rgmii_rxd0>;
		pinctrl-9 = <&emac_rgmii_rxd1>;
		pinctrl-10 = <&emac_rgmii_rxd2>;
		pinctrl-11 = <&emac_rgmii_rxd3>;
		pinctrl-12 = <&emac_rgmii_rxc>;
		pinctrl-13 = <&emac_rgmii_rx_ctl>;
		pinctrl-14 = <&emac_phy_intr>;
		pinctrl-15 = <&emac_phy_reset_state>;

		snps,reset-delays-us = <0 10000 100000>;
		phy-mode = "rgmii";
	};

	qcom_pmu: qcom,pmu {
		compatible = "qcom,pmu";
		qcom,pmu-events-tbl =
			< 0x0008 0x0F 0xFF 0xFF >,
			< 0x0011 0x0F 0xFF 0xFF >,
			< 0x0017 0x0F 0xFF 0xFF >;
	};

	ddr_freq_table: ddr-freq-table {
		qcom,freq-tbl =
			< 297000 >,
			< 595000 >,
			< 710000 >;
	};

	qcom_dcvs: qcom,dcvs {
		compatible = "qcom,dcvs";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		qcom_ddr_dcvs_hw: ddr {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <0>;
			qcom,bus-width = <8>;
			qcom,freq-tbl = <&ddr_freq_table>;

			ddr_dcvs_sp: sp {
			compatible = "qcom,dcvs-path";
			qcom,dcvs-path-type = <0>;
			interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI_CH0>;
			};
		};
	};

	bwmon_ddr: qcom,bwmon-ddr@408000 {
		compatible = "qcom,bwmon4";
		reg = <0x408000 0x300>, <0x401000 0x200>;
		reg-names = "base", "global_base";
		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
		qcom,mport = <0>;
		qcom,hw-timer-hz = <19200000>;
		qcom,target-dev = <&qcom_ddr_dcvs_hw>;
		qcom,count-unit = <0x10000>;
	};

	qcom_memlat: qcom,memlat {
		compatible = "qcom,memlat";
		ddr {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_ddr_dcvs_hw>;
			qcom,sampling-path = <&ddr_dcvs_sp>;
			qcom,miss-ev = <0x17>;

			silver-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
				qcom,sampling-enabled;
				qcom,compute-mon;
				qcom,cpufreq-memfreq-tbl =
					< 1094400 297000 >,
					< 1248000 595000 >,
					< 1401600 710000 >;
			};
		};
	};

	msm_gpu: qcom,kgsl-3d0@1c00000 { };
};

&firmware {
	qcom_scm {
		compatible = "qcom,scm";
		qcom,dload-mode = <&tcsr 0x13000>;
	};
};


#include "qcs405-cpu.dtsi"
#include "qcs405-pinctrl.dtsi"
#include "qcs405-blsp.dtsi"
#include "pms405-rpm-regulator.dtsi"
#include "qcs405-regulator.dtsi"
#include "qcs405-dma-heaps.dtsi"
#include "pms405.dtsi"
#include "qcs405-thermal.dtsi"
#include "qcs405-usb.dtsi"
#include "qcs405-coresight.dtsi"
#include "msm-arm-smmu-qcs405.dtsi"
&blsp1_uart2_console {
	status = "ok";
};