&soc {
	/* QUPv3_3  wrapper  instance */
	qupv3_3: qcom,qupv3_3_geni_se@26c0000 {
		compatible = "qcom,geni-se-qup";
		reg = <0x26c0000 0x6000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		clock-names = "m-ahb", "s-ahb";
		clocks = <&scc SCC_QUPV3_M_HCLK_CLK>,
			<&scc SCC_QUPV3_S_HCLK_CLK>;
		iommus = <&apps_smmu 0x4e3 0x0>;
		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
		qcom,iommu-geometry = <0x40000000 0x10000000>;
		qcom,iommu-dma = "fastmap";
		status = "ok";

		qupv3_se20_i2c: i2c@2680000 {
			compatible = "qcom,i2c-geni";
			reg = <0x2680000 0x4000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "se-clk";
			clocks = <&scc SCC_QUPV3_SE0_CLK>;
			interconnect-names = "qup-core", "qup-config", "qup-memory";
			interconnects =
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se20_i2c_active>;
			pinctrl-1 = <&qupv3_se20_i2c_sleep>;
			status = "disabled";
		};

		qupv3_se21_i2c: i2c@2684000 {
			compatible = "qcom,i2c-geni";
			reg = <0x2684000 0x4000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "se-clk";
			clocks = <&scc SCC_QUPV3_SE1_CLK>;
			interconnect-names = "qup-core", "qup-config", "qup-memory";
			interconnects =
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se21_i2c_active>;
			pinctrl-1 = <&qupv3_se21_i2c_sleep>;
			status = "disabled";
		};

		qupv3_se21_spi: spi@2684000 {
			compatible = "qcom,spi-geni";
			reg = <0x2684000 0x4000>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg-names = "se_phys";
			interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "se-clk";
			clocks = <&scc SCC_QUPV3_SE1_CLK>;
			interconnect-names = "qup-core", "qup-config", "qup-memory";
			interconnects =
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se21_spi_active>;
			pinctrl-1 = <&qupv3_se21_spi_sleep>;
			spi-max-frequency = <50000000>;
			status = "disabled";
		};

		qupv3_se22_i2c: i2c@2688000 {
			compatible = "qcom,i2c-geni";
			reg = <0x2688000 0x4000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "se-clk";
			clocks = <&scc SCC_QUPV3_SE2_CLK>;
			interconnect-names = "qup-core", "qup-config", "qup-memory";
			interconnects =
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se22_i2c_active>;
			pinctrl-1 = <&qupv3_se22_i2c_sleep>;
			status = "disabled";
		};

		qupv3_se22_spi: spi@2688000 {
			compatible = "qcom,spi-geni";
			reg = <0x2688000 0x4000>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg-names = "se_phys";
			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "se-clk";
			clocks = <&scc SCC_QUPV3_SE2_CLK>;
			interconnect-names = "qup-core", "qup-config", "qup-memory";
			interconnects =
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>,
			<&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se22_spi_active>;
			pinctrl-1 = <&qupv3_se22_spi_sleep>;
			spi-max-frequency = <50000000>;
			status = "disabled";
		};
	};
};