#include <dt-bindings/clock/qcom,gcc-waipio.h>

&soc {
	pcie0: qcom,pcie@1c00000 {
		compatible = "qcom,pci-msm";

		reg = <0x01c00000 0x3000>,
			<0x01c06000 0x2000>,
			<0x60000000 0xf1d>,
			<0x60000f20 0xa8>,
			<0x60001000 0x1000>,
			<0x60100000 0x100000>;
		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";

		cell-index = <0>;
		linux,pci-domain = <0>;

		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
			<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;

		interrupt-parent = <&pcie0>;
		interrupts = <0 1 2 3 4>;
		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
				"int_d";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0xffffffff>;

		interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
				0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
				0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
				0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
				0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;

		msi-map = <0x0 &gic_its 0x5980 0x1>, /* ITS IRQ 0x5980 */
			<0x100 &gic_its 0x5981 0x20>; /* ITS IRQ 0x5981 - 0x59a1 */

		perst-gpio = <&tlmm 94 0>;
		wake-gpio = <&tlmm 96 0>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&pcie0_perst_default
				&pcie0_clkreq_default
				&pcie0_wake_default>;
		pinctrl-1 = <&pcie0_perst_default
				&pcie0_clkreq_sleep
				&pcie0_wake_default>;

		gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;
		vreg-1p8-supply = <&pm8350_l6>;
		vreg-0p9-supply = <&pm8350_l5>;
		vreg-cx-supply = <&VDD_CX_LEVEL>;
		vreg-mx-supply = <&VDD_MXA_LEVEL>;
		qcom,vreg-1p8-voltage-level = <1200000 1200000 18200>;
		qcom,vreg-0p9-voltage-level = <880000 880000 80900>;
		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
						RPMH_REGULATOR_LEVEL_NOM 0>;
		qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
						RPMH_REGULATOR_LEVEL_NOM 0>;
		qcom,bw-scale = /* Gen1 */
				<RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				19200000
				/* Gen2 */
				RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				19200000
				/* Gen3 */
				RPMH_REGULATOR_LEVEL_NOM
				RPMH_REGULATOR_LEVEL_NOM
				100000000>;

		interconnect-names = "icc_path";
		interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;

		clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_PCIE_0_AUX_CLK>,
			<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,
			<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,
			<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,
			<&clock_gcc GCC_PCIE_0_CLKREF_EN>,
			<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
			<&clock_gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
			<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
			<&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
			<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
			<&clock_gcc GCC_PCIE_0_PIPE_CLK_SRC>,
			<&clock_gcc PCIE_0_PIPE_CLK>;
		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
				"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
				"pcie_phy_refgen_clk",
				"pcie_ddrss_sf_tbu_clk",
				"pcie_aggre_noc_0_axi_clk",
				"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
				"pcie_pipe_clk_ext_src";
		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
					<0>, <0>, <0>, <0>, <100000000>,
					<0>, <0>, <0>, <0>;

		resets = <&clock_gcc GCC_PCIE_0_BCR>,
			<&clock_gcc GCC_PCIE_0_PHY_BCR>;
		reset-names = "pcie_0_core_reset",
				"pcie_0_phy_reset";

		dma-coherent;
		qcom,smmu-sid-base = <0x1c00>;
		iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
			<0x100 &apps_smmu 0x1c01 0x1>;

		qcom,boot-option = <0x1>;
		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
		qcom,drv-supported;
		qcom,drv-l1ss-timeout-us = <5000>;
		qcom,l1-2-th-scale = <2>;
		qcom,l1-2-th-value = <150>;
		qcom,slv-addr-space-size = <0x4000000>;
		qcom,ep-latency = <10>;
		qcom,num-parf-testbus-sel = <0xb9>;

		qcom,pcie-phy-ver = <104>;
		qcom,phy-status-offset = <0x214>;
		qcom,phy-status-bit = <6>;
		qcom,phy-power-down-offset = <0x240>;
		qcom,phy-sequence = <0x0240 0x03 0x0
				0x0094 0x08 0x0
				0x0154 0x34 0x0
				0x016c 0x08 0x0
				0x0058 0x0f 0x0
				0x00a4 0x42 0x0
				0x0110 0x24 0x0
				0x011c 0x03 0x0
				0x0118 0xb4 0x0
				0x010c 0x02 0x0
				0x01bc 0x11 0x0
				0x00bc 0x82 0x0
				0x00d4 0x03 0x0
				0x00d0 0x55 0x0
				0x00cc 0x55 0x0
				0x00b0 0x1a 0x0
				0x00ac 0x0a 0x0
				0x00c4 0x68 0x0
				0x00e0 0x02 0x0
				0x00dc 0xaa 0x0
				0x00d8 0xab 0x0
				0x00b8 0x34 0x0
				0x00b4 0x14 0x0
				0x0158 0x01 0x0
				0x0074 0x06 0x0
				0x007c 0x16 0x0
				0x0084 0x36 0x0
				0x0078 0x06 0x0
				0x0080 0x16 0x0
				0x0088 0x36 0x0
				0x01b0 0x1e 0x0
				0x01ac 0xca 0x0
				0x01b8 0x18 0x0
				0x01b4 0xa2 0x0
				0x0050 0x07 0x0
				0x0010 0x01 0x0
				0x001c 0x31 0x0
				0x0020 0x01 0x0
				0x0024 0xde 0x0
				0x0028 0x07 0x0
				0x0030 0x4c 0x0
				0x0034 0x06 0x0
				0x0ee4 0x20 0x0
				0x0e84 0x75 0x0
				0x0e90 0x3f 0x0
				0x115c 0x7f 0x0
				0x1160 0xff 0x0
				0x1164 0xbf 0x0
				0x1168 0x3f 0x0
				0x116c 0xd8 0x0
				0x1170 0xdc 0x0
				0x1174 0xdc 0x0
				0x1178 0x5c 0x0
				0x117c 0x34 0x0
				0x1180 0xa6 0x0
				0x1190 0x34 0x0
				0x1194 0x38 0x0
				0x10d8 0x07 0x0
				0x0e3c 0x16 0x0
				0x0e40 0x04 0x0
				0x10dc 0x00 0x0
				0x104c 0x08 0x0
				0x1050 0x08 0x0
				0x1044 0xf0 0x0
				0x11a4 0x38 0x0
				0x10cc 0xf0 0x0
				0x10f4 0x07 0x0
				0x1008 0x09 0x0
				0x1014 0x05 0x0
				0x0694 0x00 0x0
				0x0654 0x00 0x0
				0x06a8 0x0f 0x0
				0x0048 0x90 0x0
				0x0620 0xc1 0x0
				0x0388 0x77 0x0
				0x0398 0x0b 0x0
				0x02dc 0x05 0x0
				0x0200 0x00 0x0
				0x0244 0x03 0x0>;

		pcie0_rp: pcie0_rp {
			reg = <0 0 0 0 0>;
		};
	};

	pcie0_msi: qcom,pcie0_msi@0x17110040 {
		compatible = "qcom,pci-msi";
		msi-controller;
		reg = <0x17110040 0x0>;
		interrupt-parent = <&intc>;
		interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
		status = "disabled";
	};

	pcie1: qcom,pcie@1c08000 {
		compatible = "qcom,pci-msm";

		reg = <0x01c08000 0x3000>,
			<0x01c0e000 0x2000>,
			<0x40000000 0xf1d>,
			<0x40000f20 0xa8>,
			<0x40001000 0x1000>,
			<0x40100000 0x100000>;
		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";

		cell-index = <1>;
		linux,pci-domain = <1>;

		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;

		interrupt-parent = <&pcie1>;
		interrupts = <0 1 2 3 4>;
		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
				"int_d";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0xffffffff>;
		interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
				0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
				0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
				0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
				0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;

		msi-parent = <&pcie1_msi>;

		perst-gpio = <&tlmm 97 0>;
		wake-gpio = <&tlmm 99 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pcie1_perst_default
				&pcie1_clkreq_default
				&pcie1_wake_default>;

		gdsc-vdd-supply = <&gcc_pcie_1_gdsc>;
		vreg-1p8-supply = <&pm8350_l6>;
		vreg-0p9-supply = <&pm8450_l2>;
		vreg-cx-supply = <&VDD_CX_LEVEL>;
		vreg-mx-supply = <&VDD_MXA_LEVEL>;
		qcom,target-link-speed = <3>; /* Set max link speed to Gen3 */

		qcom,vreg-1p8-voltage-level = <1200000 1200000 26100>;
		qcom,vreg-0p9-voltage-level = <880000 912000 193000>;
		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
						RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
		qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
						RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
		qcom,bw-scale = /* Gen1 */
				<RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				19200000
				/* Gen2 */
				RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				19200000
				/* Gen3 */
				RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				100000000>;

		interconnect-names = "icc_path";
		interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;

		clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_PCIE_1_AUX_CLK>,
			<&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>,
			<&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>,
			<&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>,
			<&clock_gcc GCC_PCIE_1_CLKREF_EN>,
			<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
			<&clock_gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
			<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
			<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
			<&clock_gcc GCC_PCIE_1_PIPE_CLK_SRC>,
			<&clock_gcc PCIE_1_PIPE_CLK>,
			<&clock_gcc GCC_PCIE_1_PHY_AUX_CLK>;
		clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
				"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
				"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
				"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
				"pcie_phy_refgen_clk",
				"pcie_ddrss_sf_tbu_clk",
				"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
				"pcie_pipe_clk_ext_src", "pcie_phy_aux_clk";
		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
					<0>, <0>, <0>, <0>, <100000000>, <0>,
					<0>, <0>, <0>, <0>;

		resets = <&clock_gcc GCC_PCIE_1_BCR>,
			<&clock_gcc GCC_PCIE_1_PHY_BCR>;
		reset-names = "pcie_1_core_reset",
				"pcie_1_phy_reset";

		dma-coherent;
		qcom,smmu-sid-base = <0x1c80>;
		iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
			<0x100 &apps_smmu 0x1c81 0x1>;

		qcom,boot-option = <0x1>;
		qcom,aux-clk-freq = <17>; /* 16.6 MHz */
		qcom,eq-fmdc-t-min-phase23 = <1>;
		qcom,slv-addr-space-size = <0x20000000>;
		qcom,ep-latency = <10>;
		qcom,num-parf-testbus-sel = <0xb9>;
		qcom,l1-2-th-scale = <2>;
		qcom,l1-2-th-value = <150>;

		qcom,pcie-phy-ver = <105>;
		qcom,phy-status-offset = <0x1214>;
		qcom,phy-status-bit = <7>;
		qcom,phy-power-down-offset = <0x1240>;
		qcom,phy-sequence = <0x1240 0x03 0x0
				0x101c 0x31 0x0
				0x1020 0x01 0x0
				0x1024 0xde 0x0
				0x1028 0x07 0x0
				0x1030 0x97 0x0
				0x1034 0x0c 0x0
				0x1044 0x14 0x0
				0x1048 0x90 0x0
				0x1058 0x0f 0x0
				0x1074 0x06 0x0
				0x1078 0x06 0x0
				0x107c 0x16 0x0
				0x1080 0x16 0x0
				0x1084 0x36 0x0
				0x1088 0x36 0x0
				0x1094 0x08 0x0
				0x10a4 0x46 0x0
				0x10a8 0x04 0x0
				0x10ac 0x0a 0x0
				0x10b0 0x1a 0x0
				0x10b4 0x14 0x0
				0x10b8 0x34 0x0
				0x10bc 0x82 0x0
				0x10c4 0xd0 0x0
				0x10cc 0x55 0x0
				0x10d0 0x55 0x0
				0x10d4 0x03 0x0
				0x10d8 0x55 0x0
				0x10dc 0x55 0x0
				0x10e0 0x05 0x0
				0x110c 0x02 0x0
				0x1154 0x34 0x0
				0x1158 0x12 0x0
				0x115c 0x00 0x0
				0x1168 0x0a 0x0
				0x116c 0x04 0x0
				0x119c 0x88 0x0
				0x1174 0x20 0x0
				0x117c 0x06 0x0
				0x11a0 0x14 0x0
				0x11a8 0x0f 0x0
				0x0220 0x16 0x0
				0x03c0 0x38 0x0
				0x0a20 0x16 0x0
				0x0bc0 0x38 0x0
				0x0364 0xcc 0x0
				0x0368 0x12 0x0
				0x036c 0xcc 0x0
				0x0374 0x4a 0x0
				0x0378 0x29 0x0
				0x037c 0xc5 0x0
				0x0380 0xad 0x0
				0x0384 0xb6 0x0
				0x0388 0xc0 0x0
				0x038c 0x1f 0x0
				0x0390 0xfb 0x0
				0x0394 0x0f 0x0
				0x0398 0xc7 0x0
				0x039c 0xef 0x0
				0x03a0 0xbf 0x0
				0x03a4 0xa0 0x0
				0x03a8 0x81 0x0
				0x03ac 0xde 0x0
				0x03b0 0x7f 0x0
				0x0b64 0xcc 0x0
				0x0b68 0x12 0x0
				0x0b6c 0xcc 0x0
				0x0b74 0x4a 0x0
				0x0b78 0x29 0x0
				0x0b7c 0xc5 0x0
				0x0b80 0xad 0x0
				0x0b84 0xb6 0x0
				0x0b88 0xc0 0x0
				0x0b8c 0x1f 0x0
				0x0b90 0xfb 0x0
				0x0b94 0x0f 0x0
				0x0b98 0xc7 0x0
				0x0b9c 0xef 0x0
				0x0ba0 0xbf 0x0
				0x0ba4 0xa0 0x0
				0x0ba8 0x81 0x0
				0x0bac 0xde 0x0
				0x0bb0 0x7f 0x0
				0x03b4 0x20 0x0
				0x022c 0x3f 0x0
				0x0230 0x37 0x0
				0x0bb4 0x20 0x0
				0x0a2c 0x3f 0x0
				0x0a30 0x37 0x0
				0x0078 0x05 0x0
				0x007c 0xf6 0x0
				0x0878 0x05 0x0
				0x087c 0xf6 0x0
				0x0290 0x05 0x0
				0x0a90 0x05 0x0
				0x03f8 0x1f 0x0
				0x0400 0x1f 0x0
				0x0408 0x1f 0x0
				0x0410 0x1f 0x0
				0x0418 0x1f 0x0
				0x0420 0x1f 0x0
				0x03f4 0x1f 0x0
				0x03fc 0x1f 0x0
				0x0404 0x1f 0x0
				0x0bf8 0x1f 0x0
				0x0c00 0x1f 0x0
				0x0c08 0x1f 0x0
				0x0c10 0x1f 0x0
				0x0c18 0x1f 0x0
				0x0c20 0x1f 0x0
				0x0bf4 0x1f 0x0
				0x0bfc 0x1f 0x0
				0x0c04 0x1f 0x0
				0x0208 0x0c 0x0
				0x0a08 0x0c 0x0
				0x020c 0x0a 0x0
				0x0a0c 0x0a 0x0
				0x02dc 0x0a 0x0
				0x0adc 0x0a 0x0
				0x0308 0x0b 0x0
				0x0b08 0x0b 0x0
				0x027c 0x10 0x0
				0x0a7c 0x10 0x0
				0x02b4 0x00 0x0
				0x0ab4 0x00 0x0
				0x02ec 0x0f 0x0
				0x0aec 0x0f 0x0
				0x02c4 0x00 0x0
				0x02c8 0x1f 0x0
				0x0ac4 0x00 0x0
				0x0ac8 0x1f 0x0
				0x0030 0x1a 0x0
				0x0034 0x0c 0x0
				0x0830 0x1a 0x0
				0x0834 0x0c 0x0
				0x141c 0xc1 0x0
				0x1490 0x00 0x0
				0x13e0 0x16 0x0
				0x13e4 0x22 0x0
				0x1508 0x02 0x0
				0x14a0 0x16 0x0
				0x1584 0x28 0x0
				0x1370 0x2e 0x0
				0x155c 0x2e 0x0
				0x1388 0x99 0x0
				0x1200 0x00 0x0
				0x1244 0x03 0x0>;

		pcie1_rp: pcie1_rp {
			reg = <0 0 0 0 0>;
		};
	};

	pcie1_msi: qcom,pcie1_msi@17110040 {
		compatible = "qcom,pci-msi";
		msi-controller;
		reg = <0x17110040 0x0>;
		interrupt-parent = <&intc>;
		interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
	};
};