QTI Global Distributed Switch Controller (GDSC) Regulator Driver

The GDSC driver, implemented under the regulator framework, is responsible for
safely collapsing and restoring power to peripheral and multimedia cores on
chipsets like SDM845 for power savings.

Required properties:
 - compatible:      Must be "qcom,gdsc"
 - regulator-name:  A string used as a descriptive name for regulator outputs
 - reg:             The address of the GDSCR register

Optional properties:
 - parent-supply:   phandle to the parent supply/regulator node
 - clock-names:     List of string names for core clocks
 - qcom,retain-regs: Presence denotes a hardware requirement to enable the
		     usage of retention registers which maintain their state
		     after the GDSC is disabled and re-enabled.
 - qcom,skip-logic-collapse: Presence denotes a requirement to leave power to
                             the core's logic enabled.
 - qcom,support-hw-trigger: Presence denotes a hardware feature to switch
			    on/off this regulator based on internal HW signals
			    to save more power.
 - qcom,enable-root-clk: Presence denotes that the clocks in the "clocks"
			property are required to be enabled before gdsc is
			turned on and disabled before turning off gdsc. This
			will be used in subsystems where reset is synchronous
			and root clk is active without sw being aware of its
			state. The clock-name which denotes the root clock
			should be named as "core_root_clk".
 - qcom,force-enable-root-clk: If set, denotes that the root clock should be
			force enabled before turning on the GDSC and then be
			immediately force disabled. Likewise for GDSC disable.
			This is used in cases where the core root clock needs
			to be force-enabled prior to turning on the core. The
			clock-name which denotes the root clock should be
			"core_root_clk".
 - qcom,clk-dis-wait-val: Input value for CLK_DIS_WAIT controls state transition
			 delay after halting clock in the collapsible core.
 - reg-names:		Names of the bases for the above "reg" registers.
			Ex. "base", "domain-addr", "sw-reset", "hw-ctrl-addr".
 - qcom,no-status-check-on-disable: Do not poll the status bit when GDSC
			is disabled.
 - qcom,gds-timeout:	Maximum time (in usecs) that might be taken by a GDSC
			to enable.
 - qcom,reset-aon-logic: If present, the GPU DEMET cells need to be reset while
			 enabling the GX GDSC.
 - vdd_parent-supply:	phandle to the regulator that this GDSC gates. If
			present, need to vote for a minimum operational voltage
			(LOW_SVS) on the GDSC parent regulator prior to
			configuring it. The vote is removed once the GDSC FSM
			has latched on to the new state.
 - resets: reset specifier pair consisting of phandle for the reset controller
			and reset lines used by this controller. These can be
			supplied only if we support qcom,skip-logic-collapse.
 - reset-names: reset signal name strings sorted in the same order as the resets
			property. These can be supplied only if we support
			qcom,skip-logic-collapse.
 - qcom,skip-disable-before-sw-enable : Presence denotes a hardware requirement
					to leave the GDSC on that has been
					enabled by an entity external to HLOS.
 - qcom,no-config-gdscr: Presence denotes HW only supports a single register
			per GDSC.
 - qcom,collapse-vote: If present, GDSC will be controlled by votable register.
			We need to pass the phandle of the register along with
			the bit number of respective GDSC.
 - sw-reset: If present, supports asynchronous resets for GDSC. We need to pass
			the phandles of reset registers while using the property.
 - domain-addr: If present, supports reset for voltage rail of GDSC. We pass
			the phandle of the register while using the property.
 - hw-ctrl-addr: If present, separate register will be there to poll for GDSC
			status. While using the property, need to pass the phandle
			of the register.
 - qcom,skip-disable: Boolean flag indicating that the gdsc must not be
			physically disabled upon a software disable request.
			Instead, the GDSC will be disabled by always-on
			processor (AOP) upon entering system sleep. The AOP
			will also perform a special reset sequence for the GDSC
			upon resuming the system sleep.
 - qcom,support-cfg-gdscr: If present, the GDSC power on/down polling status is
			read through GDSC configuration register.
 - mboxes: Mailbox tuple containing QMP mailbox phandle and channel identifier.
			If this is specified, then a QMP message should be sent
			to enable the GDSC instead of setting SW_COLLAPSE=0.
 - qcom,collapse-vote : If present, GDSC will be controlled by votable register.
			Some targets have single votable register to control GDSC,
			but there could be targets where separate votable registers
			to control the GDSCs individually for active and sleep states.

Example:
	gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
		compatible = "qcom,gdsc";
		regulator-name = "gdsc_oxili_gx";
		parent-supply = <&pm8841_s4>;
		reg = <0xfd8c4024 0x4>;
		clock-names = "core_clk";
		mboxes = <&qmp_aop 0>;
		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
	};

	/* Single votable register */
	gcc_pcie_0_gdsc: qcom,gdsc@17b004 {
		compatible = "qcom,gdsc";
		regulator-name = "gcc_pcie_0_gdsc";
		qcom,collapse-vote = <&active_ctrl 0>;
	};

	/* Multiple votable registers */
	gcc_pcie_1_gdsc: qcom,gdsc@19d004 {
		compatible = "qcom,gdsc";
		regulator-name = "gcc_pcie_1_gdsc";
		qcom,collapse-vote = <&active_ctrl &sleep_ctrl 1>;
	};