#include "sdmshrike-gpu.dtsi"

&msm_gpu {
	/* Updated chip ID */
	qcom,chipid = <0x6080001>;

	/* Power level to start throttling */
	qcom,throttle-pwrlevel = <3>;

	qcom,bus-table-ddr =
		<MHZ_TO_KBPS(0, 4)>,    /* index=0  */
		<MHZ_TO_KBPS(200, 4)>,  /* index=1  */
		<MHZ_TO_KBPS(300, 4)>,  /* index=2  */
		<MHZ_TO_KBPS(451, 4)>,  /* index=3  */
		<MHZ_TO_KBPS(547, 4)>,  /* index=4  */
		<MHZ_TO_KBPS(681, 4)>,  /* index=5  */
		<MHZ_TO_KBPS(768, 4)>, /* index=6  */
		<MHZ_TO_KBPS(1017, 4)>, /* index=7  */
		<MHZ_TO_KBPS(1353, 4)>, /* index=8  */
		<MHZ_TO_KBPS(1555, 4)>, /* index=9  */
		<MHZ_TO_KBPS(1804, 4)>, /* index=10  */
		<MHZ_TO_KBPS(2092, 4)>; /* index=11  */

	qcom,bus-table-cnoc =
		<0>,   /* Off */
		<100>; /* On */

	nvmem-cells = <&gpu_speed_bin>;
	nvmem-cell-names = "speed_bin";

	/delete-property/qcom,initial-pwrlevel;
	/delete-node/qcom,gpu-pwrlevels;
	/delete-node/qcom,gpu-pwrlevel-bins;
	qcom,gpu-pwrlevel-bins {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible="qcom,gpu-pwrlevel-bins";
		qcom,gpu-pwrlevels-0 {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,speed-bin = <0>;
			qcom,initial-pwrlevel = <1>;

			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <530000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
				qcom,bus-freq = <6>;
				qcom,bus-min = <5>;
				qcom,bus-max = <9>;
			};

			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <392000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
				qcom,bus-freq = <3>;
				qcom,bus-min = <3>;
				qcom,bus-max = <8>;
			};
		};

		qcom,gpu-pwrlevels-1 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <1>;
				qcom,initial-pwrlevel = <4>;

			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <670000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
				qcom,bus-freq = <10>;
				qcom,bus-min = <8>;
				qcom,bus-max = <11>;
			};

			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <625000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
				qcom,bus-freq = <8>;
				qcom,bus-min = <7>;
				qcom,bus-max = <9>;
			};

			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <595000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
				qcom,bus-freq = <7>;
				qcom,bus-min = <6>;
				qcom,bus-max = <11>;
			};

			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <530000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
				qcom,bus-freq = <6>;
				qcom,bus-min = <5>;
				qcom,bus-max = <9>;
			};

			qcom,gpu-pwrlevel@4 {
				reg = <4>;
				qcom,gpu-freq = <392000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
				qcom,bus-freq = <3>;
				qcom,bus-min = <3>;
				qcom,bus-max = <8>;
			};
		};

		qcom,gpu-pwrlevels-2 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <2>;
				qcom,initial-pwrlevel = <4>;

			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <670000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
				qcom,bus-freq = <10>;
				qcom,bus-min = <8>;
				qcom,bus-max = <11>;
			};

			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <625000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
				qcom,bus-freq = <8>;
				qcom,bus-min = <7>;
				qcom,bus-max = <9>;
			};

			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <595000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
				qcom,bus-freq = <7>;
				qcom,bus-min = <6>;
				qcom,bus-max = <11>;
			};

			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <530000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
				qcom,bus-freq = <6>;
				qcom,bus-min = <5>;
				qcom,bus-max = <9>;
			};

			qcom,gpu-pwrlevel@4 {
				reg = <4>;
				qcom,gpu-freq = <392000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
				qcom,bus-freq = <3>;
				qcom,bus-min = <3>;
				qcom,bus-max = <8>;
			};
		};

		qcom,gpu-pwrlevels-3 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <3>;
				qcom,initial-pwrlevel = <4>;

			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <670000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
				qcom,bus-freq = <10>;
				qcom,bus-min = <8>;
				qcom,bus-max = <11>;
			};

			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <625000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
				qcom,bus-freq = <8>;
				qcom,bus-min = <7>;
				qcom,bus-max = <9>;
			};

			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <595000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
				qcom,bus-freq = <7>;
				qcom,bus-min = <6>;
				qcom,bus-max = <11>;
			};

			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <530000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
				qcom,bus-freq = <6>;
				qcom,bus-min = <5>;
				qcom,bus-max = <9>;
			};

			qcom,gpu-pwrlevel@4 {
				reg = <4>;
				qcom,gpu-freq = <392000000>;
				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
				qcom,bus-freq = <3>;
				qcom,bus-min = <3>;
				qcom,bus-max = <8>;
			};
		};
	};

	qcom,l3-pwrlevels {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "qcom,l3-pwrlevels";

		qcom,l3-pwrlevel@0 {
			reg = <0>;
			qcom,l3-freq = <0>;
		};

		qcom,l3-pwrlevel@1 {
			reg = <1>;
			qcom,l3-freq = <1344000000>;
		};

		qcom,l3-pwrlevel@2 {
			reg = <2>;
			qcom,l3-freq = <1612800000>;
		};
	};
};

&gmu {
	reg = <0x2c6a000 0x30000>,
		<0xb290000 0x10000>,
		<0xb490000 0x10000>;
	reg-names = "kgsl_gmu_reg",
		"kgsl_gmu_pdc_cfg",
		"kgsl_gmu_pdc_seq";
};