&soc {
	csr: csr@8001000 {
		compatible = "qcom,coresight-csr";
		reg = <0x8001000 0x1000>;
		reg-names = "csr-base";

		coresight-name = "coresight-csr";
		qcom,usb-bam-support;
		qcom,hwctrl-set-support;
		qcom,set-byte-cntr-support;

		qcom,blk-size = <1>;
	};

	replicator_qdss: replicator@8046000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb909>;

		reg = <0x8046000 0x1000>;
		reg-names = "replicator-base";

		coresight-name = "coresight-replicator-qdss";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				replicator0_out_tmc_etr: endpoint {
					remote-endpoint=
					<&tmc_etr_in_replicator0>;
				};
			};

			port@2 {
				reg = <0>;
				replicator0_in_tmc_etf: endpoint {
					slave-mode;
					remote-endpoint=
						<&tmc_etf_out_replicator0>;
				};
			};
		};
	};

	tmc_etr: tmc@8048000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb961>;
		reg = <0x8048000 0x1000>,
		      <0x8064000 0x15000>;
		reg-names = "tmc-base", "bam-base";

		iommus = <&apps_smmu 0x0c0 0>,
				<&apps_smmu 0x0a0 0>;

		arm,buffer-size = <0x400000>;
		arm,scatter-gather;

		coresight-name = "coresight-tmc-etr";
		qcom,mem_support;
		usb_bam_support;
		qcom,iommu-dma = "bypass";
		qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;

		coresight-ctis = <&cti0>;
		coresight-csr = <&csr>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		interrupts = <GIC_SPI 429 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "byte-cntr-irq";

		port {
			tmc_etr_in_replicator0: endpoint {
				slave-mode;
				remote-endpoint = <&replicator0_out_tmc_etr>;
			};
		};
	};

	tmc_etf: tmc@8047000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb961>;

		reg = <0x8047000 0x1000>;
		reg-names = "tmc-base";

		coresight-name = "coresight-tmc-etf";
		coresight-ctis = <&cti0>;
		coresight-csr = <&csr>;
		arm,default-sink;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				tmc_etf_out_replicator0: endpoint {
					remote-endpoint =
						<&replicator0_in_tmc_etf>;
				};
			};

			port@1 {
				reg = <0>;
				tmc_etf_in_funnel_merg: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_merg_out_tmc_etf>;
				};
			};
		};

	};

	funnel_merg: funnel@8045000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x8045000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-merg";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_merg_out_tmc_etf: endpoint {
					remote-endpoint =
						<&tmc_etf_in_funnel_merg>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_merg_in_funnel_in0: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_in0_out_funnel_merg>;
				};
			};

			port@2 {
				reg = <1>;
				funnel_merg_in_funnel_in1: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_in1_out_funnel_merg>;
				};
			};

			port@3 {
				reg = <2>;
				funnel_merg_in_funnel_in2: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_in2_out_funnel_merg>;
				};
			};
		};
	};

	funnel_in0: funnel@8041000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x8041000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_in0_out_funnel_merg: endpoint {
					remote-endpoint =
						<&funnel_merg_in_funnel_in0>;
				};
			};

			port@1 {
				reg = <6>;
				funnel_in0_in_funnel_qatb: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_qatb_out_funnel_in0>;
				};
			};

			port@2 {
				reg = <7>;
				funnel_in0_in_stm: endpoint {
					slave-mode;
					remote-endpoint = <&stm_out_funnel_in0>;
				};
			};
		};
	};

	funnel_in1: funnel@8042000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x8042000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_in1_out_funnel_merg: endpoint {
					remote-endpoint =
						<&funnel_merg_in_funnel_in1>;
				};
			};

			port@1 {
				reg = <7>;
				funnel_in1_in_tpda_mapss: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpda_mapss_out_funnel_in1>;
				};
			};
		};
	};

	stm: stm@8002000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb962>;

		reg = <0x8002000 0x1000>,
		      <0xe280000 0x180000>;
		reg-names = "stm-base", "stm-stimulus-base";

		coresight-name = "coresight-stm";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			stm_out_funnel_in0: endpoint {
				remote-endpoint = <&funnel_in0_in_stm>;
			};
		};

	};

	funnel_in2: funnel@8043000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x8043000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in2";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_in2_out_funnel_merg: endpoint {
					remote-endpoint =
						<&funnel_merg_in_funnel_in2>;
				};
			};

			port@1 {
				reg = <2>;
				funnel_in2_in_tpdm_wcss: endpoint {
					slave-mode;
					remote-endpoint =
					    <&tpdm_wcss_out_funnel_in2>;
				};
			};

			port@2 {
				reg = <5>;
				funnel_in2_in_funnel_apss1: endpoint {
					slave-mode;
					remote-endpoint =
					    <&funnel_apss1_out_funnel_in2>;
				};
			};
		};
	};

	tpdm_wcss: tpdm@899c000 {
		compatible = "qcom,coresight-dummy";

		coresight-name = "coresight-tpdm-wcss";
		qcom,dummy-source;

		port {
			tpdm_wcss_out_funnel_in2: endpoint {
				remote-endpoint = <&funnel_in2_in_tpdm_wcss>;
			};
		};
	};

	funnel_apss1: funnel@9810000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x9810000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-apss_1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_apss1_out_funnel_in2: endpoint {
					remote-endpoint =
					    <&funnel_in2_in_funnel_apss1>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_apss1_in_funnel_apss0: endpoint {
					slave-mode;
					remote-endpoint =
					    <&funnel_apss0_out_funnel_apss1>;
				};
			};

			port@2 {
				reg = <2>;
				funnel_apss1_in_tpda_actpm: endpoint {
					slave-mode;
					remote-endpoint =
					    <&tpda_actpm_out_funnel_apss1>;
				};
			};

			port@3 {
				reg = <3>;
				funnel_apss1_in_tpda_llm_silver: endpoint {
					slave-mode;
					remote-endpoint =
					    <&tpda_llm_silver_out_funnel_apss1>;
				};
			};

			port@4 {
				reg = <4>;
				funnel_apss1_in_tpda_apss: endpoint {
					slave-mode;
					remote-endpoint =
					    <&tpda_apss_out_funnel_apss1>;
				};
			};
		};
	};

	tpda_mapss: tpda@8a04000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x8a04000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-mapss";

		qcom,tpda-atid = <76>;
		qcom,dsb-elem-size = <0 32>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_mapss_out_funnel_in1: endpoint {
					remote-endpoint =
					       <&funnel_in1_in_tpda_mapss>;
				};
			};

			port@1 {
				reg = <0>;
				tpda_mapss_in_tpdm_mapss: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_mapss_out_tpda_mapss>;
				};
			};
		};
	};

	tpdm_mapss: tpdm@8a01000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x8a01000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-mapss";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_mapss_out_tpda_mapss: endpoint {
				remote-endpoint = <&tpda_mapss_in_tpdm_mapss>;
			};
		};
	};

	tpda_apss: tpda@9862000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x9862000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-apss";

		qcom,tpda-atid = <66>;
		qcom,dsb-elem-size = <0 32>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_apss_out_funnel_apss1: endpoint {
					remote-endpoint =
					       <&funnel_apss1_in_tpda_apss>;
				};
			};

			port@1 {
				reg = <0>;
				tpda_apss_in_tpdm_apss: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_apss_out_tpda_apss>;
				};
			};
		};
	};

	tpdm_apss: tpdm@9860000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x9860000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-apss";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_apss_out_tpda_apss: endpoint {
				remote-endpoint = <&tpda_apss_in_tpdm_apss>;
			};
		};
	};

	tpda_actpm: tpda@9832000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x9832000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-actpm";

		qcom,tpda-atid = <77>;
		qcom,cmb-elem-size = <0 32>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_actpm_out_funnel_apss1: endpoint {
					remote-endpoint =
					<&funnel_apss1_in_tpda_actpm>;
				};
			};

			port@1 {
				reg = <0>;
				tpda_actpm_in_tpdm_actpm: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_actpm_out_tpda_actpm>;
				};
			};
		};
	};

	tpdm_actpm: tpdm@9830000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x9830000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-actpm";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_actpm_out_tpda_actpm: endpoint {
				remote-endpoint =
					<&tpda_actpm_in_tpdm_actpm>;
			};
		};
	};

	tpda_llm_silver: tpda@98c0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x98c0000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-llm-silver";

		qcom,tpda-atid = <72>;
		qcom,cmb-elem-size = <0 32>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_llm_silver_out_funnel_apss1: endpoint {
					remote-endpoint =
					<&funnel_apss1_in_tpda_llm_silver>;
				};
			};

			port@1 {
				reg = <0>;
				tpda_llm_silver_in_tpdm_llm_silver: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_llm_silver_out_tpda_llm_silver>;
				};
			};
		};
	};

	tpdm_llm_silver: tpdm@98a0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x98a0000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-llm-silver";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_llm_silver_out_tpda_llm_silver: endpoint {
				remote-endpoint =
					<&tpda_llm_silver_in_tpdm_llm_silver>;
			};
		};
	};

	funnel_apss0: funnel@9800000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x9800000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-apss_0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_apss0_out_funnel_apss1: endpoint {
					remote-endpoint =
					    <&funnel_apss1_in_funnel_apss0>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_apss0_in_etm0: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm0_out_funnel_apss0>;
				};
			};

			port@2 {
				reg = <1>;
				funnel_apss0_in_etm1: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm1_out_funnel_apss0>;
				};
			};

			port@3 {
				reg = <2>;
				funnel_apss0_in_etm2: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm2_out_funnel_apss0>;
				};
			};

			port@4 {
				reg = <3>;
				funnel_apss0_in_etm3: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm3_out_funnel_apss0>;
				};
			};

			port@5 {
				reg = <4>;
				funnel_apss0_in_etm4: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm4_out_funnel_apss0>;
				};
			};

			port@6 {
				reg = <5>;
				funnel_apss0_in_etm5: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm5_out_funnel_apss0>;
				};
			};

			port@7 {
				reg = <6>;
				funnel_apss0_in_etm6: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm6_out_funnel_apss0>;
				};
			};

			port@8 {
				reg = <7>;
				funnel_apss0_in_etm7: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm7_out_funnel_apss0>;
				};
			};

		};
	};

	etm0: etm@9040000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x9040000 0x1000>;
		cpu = <&CPU0>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm0_out_funnel_apss0: endpoint {
				remote-endpoint = <&funnel_apss0_in_etm0>;
			};
		};
	};

	etm1: etm@9140000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x9140000 0x1000>;
		cpu = <&CPU1>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm1_out_funnel_apss0: endpoint {
				remote-endpoint = <&funnel_apss0_in_etm1>;
			};
		};
	};

	etm2: etm@9240000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x9240000 0x1000>;
		cpu = <&CPU2>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm2";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm2_out_funnel_apss0: endpoint {
				remote-endpoint = <&funnel_apss0_in_etm2>;
			};
		};
	};

	etm3: etm@9340000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x9340000 0x1000>;
		cpu = <&CPU3>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm3";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm3_out_funnel_apss0: endpoint {
				remote-endpoint = <&funnel_apss0_in_etm3>;
			};
		};
	};

	etm4: etm@9440000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x9440000 0x1000>;
		cpu = <&CPU4>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm4";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm4_out_funnel_apss0: endpoint {
				remote-endpoint = <&funnel_apss0_in_etm4>;
			};
		};
	};

	etm5: etm@9540000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x9540000 0x1000>;
		cpu = <&CPU5>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm5";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm5_out_funnel_apss0: endpoint {
				remote-endpoint = <&funnel_apss0_in_etm5>;
			};
		};
	};

	etm6: etm@9640000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x9640000 0x1000>;
		cpu = <&CPU6>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm6";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm6_out_funnel_apss0: endpoint {
				remote-endpoint = <&funnel_apss0_in_etm6>;
			};
		};
	};

	etm7: etm@9740000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x9740000 0x1000>;
		cpu = <&CPU7>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm7";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm7_out_funnel_apss0: endpoint {
				remote-endpoint = <&funnel_apss0_in_etm7>;
			};
		};
	};

	funnel_qatb: funnel@8005000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x8005000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-qatb";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_qatb_out_funnel_in0: endpoint {
					remote-endpoint =
						<&funnel_in0_in_funnel_qatb>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_qatb_in_tpda: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpda_out_funnel_qatb>;
				};
			};

			port@2 {
				reg = <4>;
				funnel_qatb_in_funnel_monaq_1: endpoint {
					slave-mode;
					remote-endpoint =
					    <&funnel_monaq_1_out_funnel_qatb>;
				};
			};

			port@3 {
				reg = <5>;
				funnel_qatb_in_funnel_lpass: endpoint {
					slave-mode;
					remote-endpoint =
					    <&funnel_lpass_out_funnel_qatb>;
				};
			};

			port@4 {
				reg = <6>;
				funnel_qatb_in_funnel_turing_1: endpoint {
					slave-mode;
					remote-endpoint =
					    <&funnel_turing_1_out_funnel_qatb>;
				};
			};
		};
	};

	tpda: tpda@8004000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x8004000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda";

		qcom,tpda-atid = <65>;
		qcom,bc-elem-size = <10 32>,
				    <13 32>;
		qcom,tc-elem-size = <13 32>;
		qcom,dsb-elem-size = <0 32>,
				     <2 32>,
				     <3 32>,
				     <5 32>,
				     <6 32>,
				     <10 32>,
				     <11 32>,
				     <13 32>;
		qcom,cmb-elem-size = <3 64>,
				     <7 64>,
				     <13 64>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_out_funnel_qatb: endpoint {
					remote-endpoint =
						<&funnel_qatb_in_tpda>;
				};

			};

			port@1 {
				reg = <0>;
				tpda_in_tpdm_center: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_center_out_tpda>;
				};
			};

			port@2 {
				reg = <1>;
				tpda_in_funnel_gpu: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_gpu_out_tpda>;
				};
			};

			port@3 {
				reg = <3>;
				tpda_in_funnel_monaq: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_monaq_out_tpda>;
				};
			};

			port@4 {
				reg = <4>;
				tpda_in_funnel_lpass_1: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_lpass_1_out_tpda>;
				};
			};

			port@5 {
				reg = <5>;
				tpda_in_funnel_turing: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_turing_out_tpda>;
				};
			};

			port@6 {
				reg = <7>;
				tpda_in_tpdm_vsense: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_vsense_out_tpda>;
				};
			};

			port@7 {
				reg = <8>;
				tpda_in_tpdm_dcc: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_dcc_out_tpda>;
				};
			};

			port@8 {
				reg = <10>;
				tpda_in_tpdm_prng: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_prng_out_tpda>;
				};
			};

			port@9 {
				reg = <12>;
				tpda_in_tpdm_qm: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_qm_out_tpda>;
				};
			};

			port@10 {
				reg = <13>;
				tpda_in_tpdm_west: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_west_out_tpda>;
				};
			};

			port@11 {
				reg = <14>;
				tpda_in_tpdm_pimem: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_pimem_out_tpda>;
				};
			};

		};
	};

	funnel_gpu: funnel@8944000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x8944000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-gpu";

		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_gpu_out_tpda: endpoint {
					remote-endpoint =
					  <&tpda_in_funnel_gpu>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_gpu_in_tpdm_gpu: endpoint {
					slave-mode;
					remote-endpoint =
					  <&tpdm_gpu_out_funnel_gpu>;
				};
			};
		};
	};

	tpdm_gpu: tpdm@8940000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x8940000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-gpu";

		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_gpu_out_funnel_gpu: endpoint {
				remote-endpoint = <&funnel_gpu_in_tpdm_gpu>;
			};
		};
	};

	tpdm_vsense: tpdm@8840000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x8840000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-vsense";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_vsense_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_vsense>;
			};
		};
	};

	tpdm_west: tpdm@8a58000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x8a58000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-west";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_west_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_west>;
			};
		};
	};

	tpdm_dcc: tpdm@8870000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x8870000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-dcc";

		qcom,hw-enable-check;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_dcc_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_dcc>;
			};
		};
	};

	tpdm_prng: tpdm@884c000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x884c000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-prng";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_prng_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_prng>;
			};
		};
	};

	tpdm_qm: tpdm@89d0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x89d0000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-qm";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_qm_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_qm>;
			};
		};
	};

	tpdm_pimem: tpdm@8850000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x8850000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-pimem";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_pimem_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_pimem>;
			};
		};
	};

	funnel_monaq1: funnel_1@89c3000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x89c5000 0x1>,
			<0x89c3000 0x1000>;
		reg-names = "funnel-base-dummy", "funnel-base-real";

		coresight-name = "coresight-funnel-monaq1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		qcom,duplicate-funnel;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_monaq_1_out_funnel_qatb: endpoint {
					remote-endpoint =
					<&funnel_qatb_in_funnel_monaq_1>;
				};
			};

			port@1 {
				reg = <6>;
				funnel_monaq_1_in_modem_etm0: endpoint {
					slave-mode;
					remote-endpoint =
					<&modem_etm0_out_funnel_monaq_1>;
				};
			};

			port@2 {
				reg = <7>;
				funnel_monaq_1_in_funnel_modem: endpoint {
					slave-mode;
					remote-endpoint =
					    <&funnel_modem_out_funnel_monaq_1>;
				};
			};
		};
	};

	tpdm_monaq: tpdm@89c0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x89c0000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-monaq";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_monaq_out_funnel_monaq: endpoint {
				remote-endpoint =
				<&funnel_monaq_in_tpdm_monaq>;
			};
		};
	};

	funnel_modem: funnel@8832000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x8832000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-modem";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_modem_out_funnel_monaq_1: endpoint {
					remote-endpoint =
					<&funnel_monaq_1_in_funnel_modem>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_modem_in_tpda_modem_0: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpda_modem_0_out_funnel_modem>;
				};
			};

			port@2 {
				reg = <1>;
				funnel_modem_in_tpda_modem_1: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpda_modem_1_out_funnel_modem>;
				};
			};
		};
	};

	tpda_modem0: tpda@8831000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x8831000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-modem-0";

		qcom,tpda-atid = <67>;
		qcom,dsb-elem-size = <0 32>;
		qcom,cmb-elem-size = <0 64>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_modem_0_out_funnel_modem: endpoint {
					remote-endpoint =
					<&funnel_modem_in_tpda_modem_0>;
				};
			};

			port@1 {
				reg = <0>;
				tpda_modem_0_in_tpdm_modem_0: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_modem_0_out_tpda_modem_0>;
				};
			};
		};
	};

	tpda_modem1: tpda@8833000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x8833000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-modem-1";

		qcom,tpda-atid = <98>;
		qcom,dsb-elem-size = <0 32>;
		qcom,cmb-elem-size = <0 64>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_modem_1_out_funnel_modem: endpoint {
					remote-endpoint =
						<&funnel_modem_in_tpda_modem_1>;
				};
			};

			port@1 {
				reg = <0>;
				tpda_modem_1_in_tpdm_modem_1: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_modem_1_out_tpda_modem_1>;
				};
			};
		};
	};

	tpdm_modem1: tpdm@8834000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x8834000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-modem-1";

		qcom,cmb-msr-skip;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_modem_1_out_tpda_modem_1: endpoint {
				remote-endpoint =
					<&tpda_modem_1_in_tpdm_modem_1>;
			};
		};
	};

	tpdm_modem0: tpdm@8830000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x8830000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-modem-0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_modem_0_out_tpda_modem_0: endpoint {
				remote-endpoint =
					<&tpda_modem_0_in_tpdm_modem_0>;
			};
		};
	};

	funnel_monaq: funnel@89c3000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x89c3000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-monaq";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_monaq_out_tpda: endpoint {
					remote-endpoint =
					    <&tpda_in_funnel_monaq>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_monaq_in_tpdm_monaq: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_monaq_out_funnel_monaq>;
				};
			};
		};
	};

	funnel_turing: funnel@8861000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x8861000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-turing";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_turing_out_tpda: endpoint {
					remote-endpoint =
					    <&tpda_in_funnel_turing>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_turing_in_tpdm_turing: endpoint {
					slave-mode;
					remote-endpoint =
					    <&tpdm_turing_out_funnel_turing>;
				};
			};
		};
	};

	tpdm_turing: tpdm@8860000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x8860000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-turing";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,msr-fix-req;

		port {
			tpdm_turing_out_funnel_turing: endpoint {
				remote-endpoint =
				    <&funnel_turing_in_tpdm_turing>;
			};
		};
	};

	funnel_turing1: funnel_1@8861000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x8868010 0x10>,
			<0x8861000 0x1000>;
		reg-names = "funnel-base-dummy", "funnel-base-real";

		coresight-name = "coresight-funnel-turing1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		qcom,duplicate-funnel;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_turing_1_out_funnel_qatb: endpoint {
					remote-endpoint =
					    <&funnel_qatb_in_funnel_turing_1>;
				};
			};

			port@1 {
				reg = <1>;
				funnel_turing_1_in_turing_etm0: endpoint {
					slave-mode;
					remote-endpoint =
					    <&turing_etm0_out_funnel_turing_1>;
				};
			};
		};
	};

	funnel_lpass: funnel@8981000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x8981000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-lpass";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_lpass_out_funnel_qatb: endpoint {
					remote-endpoint =
					    <&funnel_qatb_in_funnel_lpass>;
				};
			};

			port@1 {
				reg = <1>;
				funnel_lpass_in_audio_etm0: endpoint {
					slave-mode;
					remote-endpoint =
					    <&audio_etm0_out_funnel_lpass>;
				};
			};
		};
	};

	funnel_lpass_1: funnel_1@8981000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;

		reg = <0x8982000 0x1>,
			<0x8981000 0x1000>;
		reg-names = "funnel-base-dummy", "funnel-base-real";

		coresight-name = "coresight-funnel-lpass-1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,duplicate-funnel;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_lpass_1_out_tpda: endpoint {
					remote-endpoint =
					    <&tpda_in_funnel_lpass_1>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_lpass_1_in_tpdm_lpass: endpoint {
					slave-mode;
					remote-endpoint =
					    <&tpdm_lpass_out_funnel_lpass_1>;
				};
			};
		};
	};

	tpdm_center: tpdm@8b58000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x8b58000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-center";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,msr-fix-req;

		port {
			tpdm_center_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_center>;
			};
		};
	};

	tpdm_lpass: tpdm@8980000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x8980000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-lpass";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,msr-fix-req;

		port {
			tpdm_lpass_out_funnel_lpass_1: endpoint {
				remote-endpoint =
				<&funnel_lpass_1_in_tpdm_lpass>;
			};
		};
	};

	turing_etm0 {
		compatible = "qcom,coresight-remote-etm";

		coresight-name = "coresight-turing-etm0";
		qcom,inst-id = <13>;

		port {
			turing_etm0_out_funnel_turing_1: endpoint {
				remote-endpoint =
					<&funnel_turing_1_in_turing_etm0>;
			};
		};
	};

	modem_etm0 {
		compatible = "qcom,coresight-remote-etm";

		coresight-name = "coresight-modem-etm0";
		qcom,inst-id = <2>;

		port {
			modem_etm0_out_funnel_monaq_1: endpoint {
				remote-endpoint =
					<&funnel_monaq_1_in_modem_etm0>;
			};
		};
	};

	audio_etm0 {
		compatible = "qcom,coresight-remote-etm";

		coresight-name = "coresight-audio-etm0";
		qcom,inst-id = <5>;

		port {
			audio_etm0_out_funnel_lpass: endpoint {
				remote-endpoint =
					<&funnel_lpass_in_audio_etm0>;
			};
		};
	};

	cti0: cti@8010000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8010000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti1: cti@8011000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8011000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti2: cti@8012000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8012000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti2";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti3: cti@8013000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8013000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti3";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti4: cti@8014000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8014000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti4";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti5: cti@8015000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8015000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti5";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti6: cti@8016000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8016000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti6";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti7: cti@8017000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8017000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti7";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti8: cti@8018000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8018000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti8";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti9: cti@8019000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8019000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti9";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti10: cti@801a000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x801a000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti10";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti11: cti@801b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x801b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti11";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti12: cti@801c000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x801c000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti12";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti13: cti@801d000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x801d000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti13";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti14: cti@801e000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x801e000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti14";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti15: cti@801f000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x801f000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti15";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti_cpu0: cti@9020000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x9020000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu0";
		cpu = <&CPU0>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti_cpu1: cti@9120000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x9120000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu1";
		cpu = <&CPU1>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cpu2: cti@9220000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x9220000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu2";
		cpu = <&CPU2>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cpu3: cti@9320000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x9320000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu3";
		cpu = <&CPU3>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cpu4: cti@9420000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x9420000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu4";
		cpu = <&CPU4>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cpu5: cti@9520000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x9520000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu5";
		cpu = <&CPU5>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cpu6: cti@9620000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x9620000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu6";
		cpu = <&CPU6>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cpu7: cti@9720000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x9720000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu7";
		cpu = <&CPU7>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	hwevent: hwevent@4506604 {
		compatible = "qcom,coresight-hwevent";
		reg = <0x04506604 0x4>;

		reg-names = "ddr-ch0-cfg";

		coresight-name = "coresight-hwevent";
		coresight-csr = <&csr>;
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	apss_tgu: tgu@9900000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b999>;
		reg = <0x09900000 0x1000>;
		reg-names = "tgu-base";
		tgu-steps = <3>;
		tgu-conditions = <4>;
		tgu-regs = <8>;
		tgu-timer-counters = <8>;
		interrupts = <0 53 1>, <0 54 1>, <0 55 1>, <0 56 1>;
		coresight-name = "coresight-tgu-apss";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti0_apss: cti@98e0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x98e0000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-apss_cti0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti1_apss: cti@98f0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x98f0000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-apss_cti1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti0_dlct: cti@8b59000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8b59000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlct_cti0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti1_dlct: cti@8b5a000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8b5a000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlct_cti1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti2_dlct: cti@8b5b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8b5b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlct_cti2";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti3_dlct: cti@8b5c000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8b5c000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlct_cti3";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_arm9: cti@8b50000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8b50000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-arm9_cti";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cortex_m3: cti@8b30000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8b30000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cortex_m3";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_dlmt_cti0: cti@89c1000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x89c1000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlmt_cti0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_gpu_isdb_cti: cti@8941000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8941000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-gpu_isdb_cti";

		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
			<&gpucc GPU_CC_CX_APB_CLK>;
		clock-names = "apb_pclk", "gpu_apb_clk";
		qcom,proxy-clks = "gpu_apb_clk";

		//vddcx-supply = <&gpu_cx_gdsc>;
		//vdd-supply = <&gpu_gx_gdsc>;
		regulator-names = "vddcx", "vdd";
		qcom,proxy-regs  = "vddcx", "vdd";
	};

	cti_lpass_q6_cti: cti@8987000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8987000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-lpass_q6_cti";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_mapss_cti: cti@8a02000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8a02000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-mapss_cti";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_mss_q6_cti: cti@883b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x883b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-mss_q6_cti";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_turing_q6_cti: cti@8867000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0x8867000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-turing_q6_cti";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_wcss_cti0: cti@cadc000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0xcadc000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-wcss_cti0";
		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_wcss_cti1: cti@cadd000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0xcadd000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-wcss_cti1";
		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_wcss_cti2: cti@cade000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb906>;
		reg = <0xcade000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-wcss_cti2";
		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};
};