102 lines
3.3 KiB
Text
102 lines
3.3 KiB
Text
== Introduction==
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LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
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that can be shared by multiple clients. Clients here are different cores in the
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SOC, the idea is to minimize the local caches at the clients and migrate to
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common pool of memory. Cache memory is divided into partitions called slices
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which are assigned to clients. Clients can query the slice details, activate
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and deactivate them.
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Properties:
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be "qcom,sdm845-llcc" or "qcom,sm8150-llcc" or
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"qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,waipio-llcc"
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or "qcom,sdxlemur-llcc" or "qcom,diwali-llcc"
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or "qcom,kalama-llcc" or "qcom,cinder-llcc"
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or "qcom,sdmshrike-llcc" or "qcom,lemans-llcc"
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or "qcom,crow-llcc" or "qcom,kona-llcc".
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"qcom,llcc-v2" must be appended for V2 hardware or
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"qcom,llcc-v21" for V2.1 or "qcom,llcc-v31" for V3.1 or
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"qcom,llcc-v41" for V4.1 or "qcom,llcc-v50" for V5.0.
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- reg:
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Usage: required
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Value Type: <prop-encoded-array>
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Definition: The first element specifies the llcc base start address and
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the size of the register region. The second element specifies
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the llcc broadcast base address and size of the register region.
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The third element is optional and specifies the feature register
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used to decide which llcc configuration to use if multiple are
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available.
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- reg-names:
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Usage: required
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Value Type: <stringlist>
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Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".
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The third element is needed only if multiple llcc configurations
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are available and must be "multi_ch_reg".
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- interrupts:
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Usage: required
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Definition: The interrupt is associated with the llcc edac device.
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It's used for llcc cache single and double bit error detection
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and reporting.
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- multi-ch-off:
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Usage: optional
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Value Type: <prop-encoded-array>
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Definition: If this exists, then the device has the potential to be configured
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with different numbers of ddr channels at runtime. The value here
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specifies the offset in bits into the "multi_ch_reg" register and
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and the number of bits used to decied which llcc configuration to
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use.
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- max-banks
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Usage: optional
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Value Type: <prop-encoded-array>
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Definition: If this exists, then the device has a potential to only use a
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certain number of banks. This caps the number of banks used
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at the value set.
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Example:
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cache-controller@1100000 {
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compatible = "qcom,sdm845-llcc";
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reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
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reg-names = "llcc_base", "llcc_broadcast_base";
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interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
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};
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LLCC Performance Monitor
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===
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be "qcom,llcc-perfom"
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: List of phandles and clock specifier pairs for the llcc perfmon
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trace feature support.
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: List of clock input name strings sorted in the same
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order as the clocks property. Definition must have
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"qdss_clk"
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Example:
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cache-controller@1100000 {
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...
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llcc-perfmon {
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compatible = "qcom,llcc-perfmon";
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clocks = <&aoss_qmp QDSS_CLK>;
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clock-names = "qdss_clk";
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};
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...
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};
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