23 lines
665 B
Text
23 lines
665 B
Text
* ARM Performance Monitor Units
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ARM cores often have a PMU for counting cpu and cache events like cache misses
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and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
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representation in the device tree should be done as under:-
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Required properties:
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- compatible : should be one of
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"arm,armv8-pmuv3"
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- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
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interrupt (PPI) then 1 interrupt should be specified.
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Optional properties:
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- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
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events.
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Example:
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pmu {
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compatible = "arm,armv8-pmu3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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