60 lines
1.7 KiB
Text
60 lines
1.7 KiB
Text
Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding
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--------------------------------------------------------------------
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Required properties :
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- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc",
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"qcom,sdm845-v2-gpucc"
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"qcom,lahaina-gpucc",
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"qcom,shima-gpucc",
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"qcom,holi-gpucc".
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"qcom,waipio-gpucc",
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"qcom,waipio-gpucc-v2",
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"qcom,diwali-gpucc",
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"qcom,kalama-gpucc"
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"qcom,sm8150-gpucc",
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"qcom,sm8250-gpucc",
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"qcom,sa8155-gpucc",
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"qcom,khaje-gpucc",
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"qcom,sc8180x-gpucc".
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"qcom,monaco-gpucc",
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"qcom,scuba-gpucc"
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"qcom,lemans-gpucc"
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"qcom,crow-gpucc"
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"qcom,monaco_auto-gpucc"
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"qcom,trinket-gpucc"
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"qcom,sdm670-gpucc"
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- reg: shall contain base register offset and size.
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- reg-names: names of registers listed in the same order as in the reg property.
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Must contain "cc_base".
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- vdd_mx-supply: The vdd_mx logic rail supply.
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- #clock-cells : from common clock binding, shall contain 1
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- #reset-cells : from common reset binding, shall contain 1
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Optional properties :
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- #power-domain-cells : from generic power domain binding, shall contain 1
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- clocks : shall contain the XO clock
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shall contain the gpll0 out main clock (msm8998)
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- clock-names : shall be "xo"
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shall be "gpll0" (msm8998)
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Example:
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1.
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gpucc: clock-controller@5090000 {
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compatible = "qcom,sdm845-gpucc";
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reg = <0x5090000 0x9000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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};
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2.
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clock_gpucc: clock-controller@3d90000 {
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compatible = "qcom,lahaina-gpucc";
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reg = <0x3d90000 0x9000>;
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reg-names = "cc_base";
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vdd_mx-supply = <&VDD_MXA_LEVEL>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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