80 lines
2.3 KiB
Text
80 lines
2.3 KiB
Text
Qualcomm Technologies, Inc. GPU powerlevels
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Powerlevels are defined in sets by qcom,gpu-pwrlevels. Multiple sets (bins)
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can be defined within qcom,gpu-pwrelvel-bins. Each powerlevel defines a
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voltage, bus, bandwidth level, and a DVM value.
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- qcom,gpu-pwrlevel-bins: Contains one or more qcom,gpu-pwrlevels sets
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Properties:
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- compatible: Must be qcom,gpu-pwrlevel-bins
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- qcom,gpu-pwrlevels: Defines a set of powerlevels
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Properties:
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- qcom,speed-bin: Speed bin identifier for the set - must match
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the value read from the hardware
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- qcom,initial-pwrlevel: GPU wakeup powerlevel
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- qcom,gpu-pwrlevel: A single powerlevel
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- qcom,ca-target-pwrlevel:
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This value indicates which qcom,gpu-pwrlevel
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to jump on in case of context aware power level
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jump.
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Required Properties:
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- reg: Index of the powerlevel (0 = highest perf)
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- qcom,gpu-freq GPU frequency for the powerlevel (in Hz)
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- qcom,bus-freq Index to a bus level (defined by the bus
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settings).
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- qcom,bus-freq-ddrX If specified, define the DDR specific bus
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frequency for the power level. X will be the
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return value from of_fdt_get_ddrtype().
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Optional Properties:
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- qcom,bus-min Minimum bus level to set for the power level
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- qcom,bus-min-ddrX If specified, define the DDR specific minimum
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bus level for the power level. X will be the
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return value from of_fdt_get_ddrtype().
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- qcom,bus-max maximum bus level to set for the power level
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- qcom,bus-max-ddrX If specified, define the DDR specific maximum
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bus level for the power level. X will be the
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return value from of_fdt_get_ddrtype().
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- qcom,acd-level: Value that is used as a register setting for
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the ACD power feature. It helps to determine
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the threshold for when ACD activates. Zero is
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the default value, and the setting where ACD
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will never activate.
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Example:
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <0>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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qcom,acd-level = <0xffffffff>;
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};
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Example for DDR4/DDR5 specific part:
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <480000000>;
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/* DDR5 */
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qcom,bus-freq-ddr8 = <10>;
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qcom,bus-min-ddr8 = <9>;
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qcom,bus-max-ddr8 = <11>;
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/* DDR 4 */
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qcom,bus-freq-ddr7 = <9>;
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qcom,bus-min-ddr7 = <7>;
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qcom,bus-max-ddr7 = <9>;
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qcom,acd-level = <0xffffffff>;
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};
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