26 lines
881 B
Text
26 lines
881 B
Text
Qualcomm Technologies, Inc. EPSS L3 interconnect driver binding
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The EPSS L3 Interconnect provider supports the scaling of L3 cache
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performance states of the CPU subsystem.
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Required properties :
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- compatible : shall contain only one of the following:
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"qcom,cinder-epss-l3-cpu",
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"qcom,lahaina-epss-l3-cpu";
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- reg : Address and length of the register set for the device
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- clock-names: should contain "xo", "alternate"
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- clocks: list of phandle and clock specifier pairs corresponding to
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entries in the clock-names property.
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- #interconnect-cells : should contain 1
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Examples:
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epss_l3_cpu: l3_cpu@18590000{
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reg = <0x18590000 0x4000>;
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compatible = "qcom,lahaina-epss-l3-cpu";
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#interconnect-cells = <1>;
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clock-names = "xo", "alternate";
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clocks = <&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_GPLL0>;
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};
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