228 lines
5.5 KiB
Text
228 lines
5.5 KiB
Text
* Qualcomm Technologies, Inc. MSM NPU
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NPU (Neural Network Processing Unit) applies neural network processing
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Required properties:
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- compatible: Must be "qcom,msm-npu"
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- reg: Specify offset and length of the device register sets.
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- reg-names: Names corresponding to the defined register sets.
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- "npu_base": npu base registers
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- interrupts: Specify the npu interrupts.
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- interrupt-names: should specify relevant names to each interrupts
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property defined.
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- cache-slice-names: A set of names that identify the usecase names of a
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client that uses cache slice. These strings are used to look up the
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cache slice entries by name
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- cache-slices: The tuple has phandle to llcc device as the first argument
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and the second argument is the usecase id of the client
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- clocks: clocks required for the device.
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- clock-names: names of clocks required for the device.
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- vdd-supply: Phandle for vdd regulator device node
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- vdd_'reg'-supply: Reference to the regulator that supplies the corresponding
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'reg' domain, e.g. vdd_cx-supply.
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- qcom,proxy-reg-names: Names of the regulators that need to be turned on/off
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during proxy voting/unvoting.
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- qcom,vdd_'reg'-uV-uA: Voltage and current values for the 'reg' regulator,
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e.g. qcom,vdd_cx-uV-uA.
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- mboxes: Phandle array for mailbox controllers to be used for IPC
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- mbox-names: names of each mailboxes
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- #cooling-cells: Should be set to 2
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- qcom,npubw-dev: a phandle to a device representing bus bandwidth requirements
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(see devbw.txt)
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- qcom,npu-pwrlevels: Container for NPU power levels
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(see msm-npu-pwrlevels.txt)
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Example:
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msm_npu: qcom,msm_npu@9800000 {
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compatible = "qcom,msm-npu";
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status = "ok";
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reg = <0x9800000 0x800000>;
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reg-names = "npu_base";
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interrupts = <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>;
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iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>;
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cache-slice-names = "npu";
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cache-slices = <&llcc 23>;
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clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,
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<&clock_npucc NPU_CC_CAL_DP_CLK_SRC>,
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<&clock_npucc NPU_CC_XO_CLK>,
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<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,
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<&clock_npucc NPU_CC_BTO_CORE_CLK>,
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<&clock_npucc NPU_CC_BWMON_CLK>,
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<&clock_npucc NPU_CC_CAL_DP_CDC_CLK>,
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<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,
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<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>,
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<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,
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<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,
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<&clock_npucc NPU_CC_NPU_CORE_CLK>,
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<&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>,
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<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,
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<&clock_npucc NPU_CC_NPU_CPC_CLK>,
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<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,
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<&clock_npucc NPU_CC_PERF_CNT_CLK>,
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<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,
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<&clock_npucc NPU_CC_SLEEP_CLK>;
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clock-names = "cal_dp_clk",
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"cal_dp_clk_src",
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"xo_clk",
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"armwic_core_clk",
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"bto_core_clk",
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"bwmon_clk",
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"cal_dp_cdc_clk",
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"comp_noc_axi_clk",
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"conf_noc_ahb_clk",
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"npu_core_apb_clk",
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"npu_core_atb_clk",
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"npu_core_clk",
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"npu_core_clk_src",
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"npu_core_cti_clk",
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"npu_cpc_clk",
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"npu_cpc_timer_clk",
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"perf_cnt_clk",
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"qtimer_core_clk",
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"sleep_clk";
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vdd-supply = <&npu_core_gdsc>;
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vdd_cx-supply = <&pm8150l_s6_level>;
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qcom,proxy-reg-names ="vdd", "vdd_cx";
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qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
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mboxes = <&qmp_npu0 0>, <&qmp_npu1 0>;
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mbox-names = "npu_low", "npu_high";
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#cooling-cells = <2>;
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qcom,npubw-dev = <&npu_npu_ddr_bw>;
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qcom,npu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,npu-pwrlevels";
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initial-pwrlevel = <4>;
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qcom,npu-pwrlevel@0 {
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reg = <0>;
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clk-freq = <9600000
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9600000
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19200000
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19200000
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19200000
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19200000
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9600000
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60000000
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19200000
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19200000
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30000000
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19200000
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19200000
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19200000
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19200000
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19200000
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9600000
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19200000
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0>;
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};
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qcom,npu-pwrlevel@1 {
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reg = <1>;
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clk-freq = <300000000
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300000000
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19200000
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100000000
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19200000
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19200000
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300000000
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150000000
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19200000
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19200000
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60000000
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100000000
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100000000
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37500000
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100000000
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19200000
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300000000
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19200000
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0>;
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};
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qcom,npu-pwrlevel@2 {
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reg = <2>;
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clk-freq = <350000000
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350000000
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19200000
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150000000
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19200000
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19200000
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350000000
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200000000
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37500000
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19200000
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120000000
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150000000
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150000000
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75000000
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150000000
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19200000
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350000000
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19200000
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0>;
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};
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qcom,npu-pwrlevel@3 {
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reg = <3>;
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clk-freq = <400000000
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400000000
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19200000
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200000000
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19200000
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19200000
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400000000
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300000000
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37500000
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19200000
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120000000
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200000000
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200000000
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75000000
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200000000
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19200000
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400000000
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19200000
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0>;
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};
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qcom,npu-pwrlevel@4 {
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reg = <4>;
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clk-freq = <600000000
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600000000
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19200000
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300000000
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19200000
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19200000
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600000000
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403000000
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75000000
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19200000
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240000000
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300000000
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300000000
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150000000
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300000000
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19200000
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600000000
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19200000
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0>;
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};
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qcom,npu-pwrlevel@5 {
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reg = <5>;
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clk-freq = <715000000
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715000000
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19200000
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350000000
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19200000
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19200000
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715000000
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533000000
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75000000
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19200000
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240000000
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350000000
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350000000
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150000000
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350000000
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19200000
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715000000
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19200000
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0>;
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};
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};
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};
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