628 lines
16 KiB
Text
628 lines
16 KiB
Text
* MSM PCI express root complex
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=========
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Main node
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=========
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- compatible:
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Usage: required
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Value type: <stringlist>
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Definition: Should be "qcom,pci-msm"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: Register ranges as listed in the reg-names property
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- reg-names:
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Usage: required
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Value type: <stringlist>
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Definition: Should contain:
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- "parf" MSM specific registers
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- "phy" PCIe PHY registers
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- "dbi" DesignWare PCIe registers
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- "elbi" External local bus interface registers
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- "iatu" Internal translation unit registers
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- "config" PCIe device configuration space
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- "io" PCIe device I/O registers
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- "bars" PCIe device base address registers
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- "tcsr" (opt) PCIe clock scheme register
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- "rumi" (opt) PCIe RUMI register
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- cell-index:
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Usage: required
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Value type: <u32>
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Definition: defines root complex ID.
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- linux,pci-domain:
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Usage: required
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Value type: <u32>
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Definition: As specified in pci.txt
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- #address-cells:
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Usage: required
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Value type: <u32>
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Definition: Should be 3. As specified in designware-pcie.txt
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- #size-cells:
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Usage: required
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Value type: <u32>
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Definition: Should be 2. As specified in designware-pcie.txt
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- ranges:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: As specified in designware-pcie.txt
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- interrupt-parent:
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Usage: required
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Value type: <phandle>
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Definition: Phandle of the interrupt controller that services
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interrupts for this device
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: PCIe root complex related interrupts
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- interrupt-names:
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Usage: required
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Value type: <stringlist>
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Definition: Should contain
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- "int_global_int"
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- "int_a"
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- "int_b"
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- "int_c"
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- "int_d",
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- #interrupt-cells:
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Usage: required
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Value type: <u32>
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Definition: Should be 1. As specified in designware-pcie.txt
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- interrupt-map-mask:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: As specified in designware-pcie.txt
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- interrupt-map:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: As specified in designware-pcie.txt
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- msi-parent:
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Usage: required
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Value type: <phandle>
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Definition: As specified in pci-msi.txt
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- <name>-gpio:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: List of phandle and GPIO specifier pairs. Should contain:
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- "perst-gpio" PCIe reset signal line
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- "wake-gpio" PCIe wake signal line
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- "qcom,ep-gpio" (opt) PCIe endpoint specific signal line
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- pinctrl-names:
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Usage: required
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Value type: <stringlist>
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Definition: Name of pin configuration groups. Should contain:
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- "default"
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- "sleep" (opt)
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- pinctrl-<num>:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: As specified in pinctrl-bindings.txt
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- <supply-name>-supply:
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Usage: required
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Value type: <phandle>
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Definition: Phandle to PCIe core and PHY power supply. Should contain:
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- "gdsc-vdd-supply" PCIe power domain control
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- "vreg-1.8-supply" power supply for PCIe PHY
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- "vreg-0.9-supply" power supply for PCIe PHY
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- "vreg-cx-supply" power supply for PCIe core
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- "vreg-3.3-supply" (opt) power supply for PCIe endpoint
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- qcom,<supply-name>-voltage-level:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: List of max/min voltage(uV) and optimal current(uA) tuple
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for power supply
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- qcom,bw-scale:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: List of CX voltage corner and rate change clock frequency
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pair for each PCIe GEN speed
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interconnect-names:
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Usage: optional
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Value type: <stringlist>
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Definition: As specified in interconnect.txt
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interconnects:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: As specified in interconnect.txt
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: List of phandle and clock specifier pairs as listed
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in clock-names property
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: List of clock names that corresponds with listed "clocks"
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- max-clock-frequency-hz:
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Usage: optional
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Value type: <u32 array>
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Definition: List of clock frequencies for each PCIe clock. Only need to
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specify the ones that needs to be changed
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- resets:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: List of phandle and reset specifier pairs as listed
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in reset-names property
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- reset-names:
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Usage: required
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Value type: <stringlist>
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Definition: Should contain:
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- "pcie_<num>_core_reset" Core reset
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- "pcie_<num>_phy_reset" PHY reset
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- qcom,smmu-sid-base:
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Usage: optional
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Value: <u32>
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Definition: Base SID for PCIe
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- iommu-map:
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Usage: optional. Required if qcom,smmu-sid-base is defined
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Value type: <prop-encoded-array>
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Definition: As defined in pci-iommu.txt. Should contain:
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- <BDF, iommu phandle, SID, 0x1>
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- qcom,target-link-speed:
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Usage: optional
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Value type: <u32>
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Definition: Override maximum GEN speed. Options:
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- 0x1 GEN 1
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- 0x2 GEN 2
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- 0x3 GEN 3
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- qcom,link-check-max-count
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Usage: optional
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Value type: <u32>
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Definition: Max number of retries for link training. Delay between each
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check is 5ms
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- qcom,boot-option:
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Usage: optional
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Value type: <u32>
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Definition: Controls PCIe bus driver boot sequence. Options:
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- BIT(0) PCIe bus driver will not start enumeration
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during its probe. Clients will control when
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PCIe bus driver should do enumeration
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- BIT(1) PCIe bus driver will not start enumeration if it
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receives a WAKE interrupt
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- qcom,drv-name:
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Usage: optional
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Value type: <string>
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Definition: Direct resource vote (DRV) is supported. APPS PCIe
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root complex driver can hand off PCIe resources to another
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subsystem. This will allow APPS to enter lower power modes
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while keeping PCIe core, PHY, and link funtional. In addition,
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the system can enter CX power collapse once the DRV subsystem
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removes its PCIe votes.
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- qcom,drv-l1ss-timeout-us:
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Usage: optional depends on qcom,drv-supported
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Value type: <u32>
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Definition: This timeout determines when DRV subsystem will put the
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link into l1ss sleep while idle in l1ss. If this is omitted,
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the default timeout is 100ms.
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- qcom,use-19p2mhz-aux-clk:
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Usage: optional
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Value type: <bool>
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Definition: Set PCIe AUX clock frequency to 19.2MHz
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- qcom,common-clk-en:
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Usage: optional
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Value type: <bool>
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Definition: Support common clock configuration
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- qcom,clk-power-manage-en:
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Usage: optional
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Value type: <bool>
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Definition: Support clock power management
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- qcom,gdsc-clk-drv-ss-nonvotable:
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Usage: optional
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Value type: <bool>
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Definition: gdsc clock can't be turned off during DRV process.
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- qcom,n-fts:
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Usage: optional
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Value type: <u32>
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Definition: Number of fast training sequences sent when the link
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transitions from L0s to L0
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- qcom,no-l0s-supported:
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Usage: optional
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Value type: <bool>
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Definition: L0s is not supported
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- qcom,no-l1-supported:
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Usage: optional
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Value type: <bool>
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Definition: L1 is not supported
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- qcom,no-l1ss-supported:
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Usage: optional
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Value type: <bool>
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Definition: L1 sub-state (L1ss) is not supported
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- qcom,apss-based-l1ss-sleep:
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Usage: optional
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Value type: <bool>
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Definition: Apss based L1ss sleep is supported
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- qcom,no-client-based-bw-voting:
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Usage: optional
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Value type: <bool>
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Definition: client based bw voting is not supported
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- qcom,no-aux-clk-sync:
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Usage: optional
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Value type: <bool>
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Definition: The AUX clock is not synchronous to the Core clock to
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support L1ss
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- qcom,l1-2-th-scale:
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Usage: optional
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Value type: <u32>
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Definition: Determines the multiplier for L1.2 LTR threshold value
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- 0 1ns
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- 1 32ns
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- 2 1us
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- 3 32us
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- 4 1ms
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- 5 32ms
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- qcom,l1-2-th-value:
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Usage: optional
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Value type: <u32>
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Definition: L1.2 LTR threshold value to be multipled with scale to
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define L1.2 latency tolerance reporting (LTR)
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- qcom,slv-addr-space-size:
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Usage: required
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Value type: <u32>
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Definition: Memory block size dedicated to PCIe root complex
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- qcom,wr-halt-size:
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Usage: optional
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Value type: <u32>
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Definition: Exponent (base 2) that determines the data size(bytes) that
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PCIe core will halt for each write
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- qcom,tlp-rd-size:
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Usage: optional
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Value type: <u32>
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Definition: Determines the maximum read request size(bytes). Options:
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- 0 128
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- 1 256
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- 2 512
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- 3 1K
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- 4 2K
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- 5 4K
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- qcom,cpl-timeout:
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Usage: optional
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Value type: <u32>
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Definition: Determines the timeout range PCIe root complex will send
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out a completion packet if no ACK is seen for TLP. Options:
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- BIT(0) 50us to 10ms
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- BIT(1) 10ms to 250ms
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- BIT(2) 250ms to 4s
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- BIT(3) 4s to 64s
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- qcom,perst-delay-us-min:
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Usage: optional
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Value type: <u32>
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Definition: Minimum allowed time(us) to sleep after asserting or
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de-asserting PERST GPI.
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- qcom,perst-delay-us-max:
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Usage: optional
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Value type: <u32>
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Definition: Maximum allowed time(us) to sleep after asserting or
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de-asserting PERST GPIO
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- qcom,ep-latency:
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Usage: optional
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Value type: <u32>
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Definition: The latency(ms) between when PCIe PHY is up and PERST is
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de-asserted. This guarantees the 100MHz clock is available for
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the PCIe devices
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- qcom,switch-latency:
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Usage: optional
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Definition: The latency(ms) between when PCIe link is up and before
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any device over the switch is accessed
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- qcom,core-preset:
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Usage: optional
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Definition: Determines how aggressive the PCIe PHY equalization is for
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Gen3 cores. The following are recommended settings:
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- short channels: 0x55555555 (default)
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- long channels: 0x77777777
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- qcom,pcie-phy-ver:
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Usage: required
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Value type: <u32>
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Definition: States the PCIe PHY version
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- qcom,phy-status-offset:
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Usage: required
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Value type: <u32>
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Definition: Offset from PCIe PHY base to check if PCIe PHY status
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- qcom,phy-status-bit:
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Usage: required
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Value type: <u32>
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Definition: BIT to check PCIe PHY status
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- qcom,phy-power-down-offset:
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Usage: required
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Value type: <u32>
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Definition: Offset from PCIe PHY base to control PHY power state
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- qcom,phy-sequence:
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Usage: required
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Value type: <prop-encoded array>
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Definition: PCIe PHY initialization sequence
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- qcom,filtered-bdfs:
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Usage: optional
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Value type: <u32 array of bdfs>
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Definition: Skip enumeration for the list of 32-bit BDFs.
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==============
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Root port node
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==============
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Root port are defined as subnodes of the PCIe controller node
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- reg:
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Usage: required
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Value type: <prop-encoded array>
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Definition: First cell is devfn, which is determined by pci bus
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topology. Assign the other cells 0 since they are not used
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- qcom,iommu-cfg:
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Usage: optional
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Value type: <u32>
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Definition: Defines PCIe root port SMMU configuration. Options:
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- BIT(0) Indicates if SMMU is present
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- BIT(1) Set IOMMU attribute S1_BYPASS
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- BIT(2) Set IOMMU attribute FAST
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- BIT(3) Set IOMMU attribute ATOMIC
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- BIT(4) Set IOMMU attribute FORCE COHERENT
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- qcom,iommu-range:
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Usage: optional
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Value type: Array of <u64>
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Definition: Pair of values describing iova base and size to allocate
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=======
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Example
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=======
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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reg = <0x1c00000 0x4000>,
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<0x1c04000 0x1000>,
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<0x60000000 0xf1d>,
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<0x60000f20 0xa8>,
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<0x60001000 0x1000>,
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<0x60100000 0x100000>,
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<0x60200000 0x100000>,
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<0x60300000 0x3d00000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
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"io", "bars", "tcsr", "rumi";
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cell-index = <0>;
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device_type = "pci";
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4 5>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d",
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc 0 140 0
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0 0 0 1 &intc 0 149 0
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0 0 0 2 &intc 0 150 0
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0 0 0 3 &intc 0 151 0
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0 0 0 4 &intc 0 152 0>;
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msi-parent = <&pcie0_msi>;
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perst-gpio = <&tlmm 35 0>;
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wake-gpio = <&tlmm 37 0>;
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qcom,ep-gpio = <&tlmm 94 0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_clkreq_default
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&pcie0_perst_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_clkreq_sleep
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&pcie0_perst_sleep
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&pcie0_wake_sleep>;
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gdsc-vdd-supply = <&pcie_0_gdsc>;
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vreg-1.8-supply = <&pm8150l_l3>;
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vreg-0.9-supply = <&pm8150_l5>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-3.3-supply = <&pm8150_l1>;
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qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;
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qcom,vreg-0.9-voltage-level = <950000 950000 24000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
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RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
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RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
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interconnect-names = "icc_path";
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interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
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clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_PCIE_0_AUX_CLK>,
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<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&clock_gcc GCC_PCIE_0_CLKREF_CLK>,
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<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
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<&clock_gcc GCC_PCIE0_PHY_REFGEN_CLK>,
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<&clock_gcc GCC_PCIE_PHY_AUX_CLK>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_tbu_clk", "pcie_phy_refgen_clk",
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"pcie_phy_aux_clk";
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max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>, <0>;
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resets = <&clock_gcc GCC_PCIE_0_BCR>,
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<&clock_gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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|
|
|
qcom,smmu-sid-base = <0x1e00>;
|
|
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
|
|
<0x100 &apps_smmu 0x1e01 0x1>;
|
|
|
|
qcom,target-link-speed = <0x2>;
|
|
qcom,link-check-max-count = <40> /* 200ms */
|
|
qcom,boot-option = <0x1>;
|
|
qcom,drv-name = "lpass";
|
|
qcom,use-19p2mhz-aux-clk;
|
|
qcom,gdsc-clk-drv-ss-nonvotable;
|
|
qcom,common-clk-en;
|
|
qcom,clk-power-manage-en;
|
|
qcom,n-fts = <0x50>;
|
|
qcom,no-l0s-supported;
|
|
qcom,no-l1-supported;
|
|
qcom,no-l1ss-supported;
|
|
qcom,no-aux-clk-sync;
|
|
qcom,slv-addr-space-size = <0x1000000>; /* 16MB */
|
|
qcom,wr-halt-size = <0xa>; /* 1KB */
|
|
qcom,tlp-rd-size = <0x5>; /* 4KB */
|
|
qcom,cpl-timeout = <0x2>; /* 10ms to 250ms */
|
|
qcom,perst-delay-us-min = <10>;
|
|
qcom,perst-delay-us-max = <15>;
|
|
qcom,ep-latency = <20>;
|
|
qcom,switch-latency = <25>;
|
|
qcom,filtered-bdfs = <0x02080000>;
|
|
|
|
qcom,core-preset = <0x55555555> /* short channel */
|
|
qcom,pcie-phy-ver = <0x2101>; /* v2 version 1.01 */
|
|
qcom,phy-status-offset = <0x814>;
|
|
qcom,phy-status-bit = <6>;
|
|
qcom,phy-power-down-offset = <0x840>;
|
|
qcom,phy-sequence = <0x0840 0x03 0x0
|
|
0x0094 0x08 0x0
|
|
0x0154 0x34 0x0
|
|
0x016c 0x08 0x0
|
|
0x0058 0x0f 0x0
|
|
0x00a4 0x42 0x0
|
|
0x0110 0x24 0x0
|
|
0x0800 0x00 0x0
|
|
0x0844 0x03 0x0>;
|
|
|
|
pcie0_rp: pcie0_rp {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
qcom,iommu-cfg = <0x3> /* SMMU PRESENT. SET S1 BYPASS */
|
|
qcom,iommu-range = <0x0 0x10000000 0x0 0x40000000>;
|
|
};
|
|
|
|
==============
|
|
i2c child node
|
|
==============
|
|
|
|
- compatible:
|
|
Usage: required
|
|
Value type: <stringlist>
|
|
Definition: Compatible list, contains
|
|
- "qcom,pcie-i2c-ntn3" for NTN3 switch attached to Root port 0
|
|
|
|
- reg:
|
|
Usage: required
|
|
Value type: <u16>
|
|
Definition: i2c slave id
|
|
|
|
- gpio-config-reg:
|
|
Usage: optional
|
|
Value type: <u32>
|
|
Definition: Slave GPIO configuration register address
|
|
|
|
- ep-reset-reg:
|
|
Usage: optional
|
|
Value type: <u32>
|
|
Definition: Slave endpoint reset register address
|
|
|
|
- ep-reset-gpio-mask:
|
|
Usage: optional
|
|
Value type: <u32>
|
|
Definition: Slave GPIO number as 32-bit mask
|
|
|
|
- dump-regs:
|
|
Usage: optional
|
|
Value Type: Array of <u32>
|
|
Definition: List of slave registers to dump by i2c read
|
|
|
|
- version-reg:
|
|
Usage: optional
|
|
Value type: <u32>
|
|
Definition: Register to find ntn3 switch version
|
|
|
|
- force-i2c-setting:
|
|
Usage: optional
|
|
Value type: <bool>
|
|
Definition: If force-i2c-setting flag is set
|
|
then de_emphasis settings are updated
|
|
irrespective of the chip version via i2c_writes
|
|
=======
|
|
Example
|
|
=======
|
|
|
|
&i2c_5 {
|
|
pcie_i2c_ctrl: pcie_i2c_ctrl {
|
|
compatible = "qcom,pcie-i2c-ntn3";
|
|
reg = <0x77>;
|
|
gpio-config-reg = <0x801208>;
|
|
ep-reset-reg = <0x801210>;
|
|
ep-reset-gpio-mask = <0xf>;
|
|
dump-regs = <0x801330 0x801350 0x801370>;
|
|
version-reg = <0x800000>;
|
|
force-i2c-setting;
|
|
};
|
|
};
|