86 lines
2.7 KiB
Text
86 lines
2.7 KiB
Text
* Data Capture and Compare (DCC)
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DCC (Data Capture and Compare) is a DMA engine, which is used to save
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configuration data or system memory contents during catastrophic failure or
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SW trigger.
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It can also perform CRC over the same configuration or memory space.
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Required properties:
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- compatible : name of the component used for driver matching, should be
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"qcom,dcc" or "qcom,dcc-v2"
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- reg : physical base address and length of the register set(s), SRAM and XPU
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of the component.
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- reg-names : names corresponding to each reg property value.
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dcc-base: Base address for DCC configuration reg
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dcc-ram-base: Start of HLOS address space in SRAM
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dcc-xpu-base: Base address for XPU configuration reg
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- dcc-ram-offset: Address offset from the start of the SRAM address space.
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Optional properties:
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- clocks: phandle reference to the parent clock.
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- clock-names: Name of the clock that needs to be enabled for the HW to run.
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Turned off when the subsystem is disabled.
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- qcom,save-reg: boolean, To save dcc registers state in memory after dcc
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enable and disable
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- link-list subnode: Each link-list subnode represents a link-list configured by default.
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It supports configure multiple link-list nodes.
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link-list subnode properties:
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- qcom,data-sink: string, To specify default data sink for dcc, should be one
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of the following:
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"atb" : To send captured data over ATB to a trace sink
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"sram" : To save captured data in dcc internal SRAM.
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- qcom,curr-link-list: int, To specify the link list to use for the default list.
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- qcom,link-list: The values to be programmed into the default link list.
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The enum values for DCC operations is defined in dt-bindings/soc/qcom,dcc_v2.h
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The following gives basic structure to be used for each operation:
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<DCC_operation addr val apb_bus>
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val is to be interpreted based on what operation is to be performed.
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Example:
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dcc: dcc@4b3000 {
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compatible = "qcom,dcc";
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reg = <0x4b3000 0x1000>,
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<0x4b4000 0x2000>,
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<0x4b0000 0x1>;
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reg-names = "dcc-base", "dcc-ram-base", "dcc-xpu-base";
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clocks = <&clock_gcc clk_gcc_dcc_ahb_clk>;
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clock-names = "dcc_clk";
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qcom,save-reg;
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link_list_0 {
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qcom,curr-link-list = <2>;
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qcom,data-sink = "sram";
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qcom,link-list = <DCC_READ 0x1740300 6 0>,
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<DCC_READ 0x1620500 4 0>,
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<DCC_READ 0x7840000 1 0>,
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<DCC_READ 0x7841010 12 0>,
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<DCC_READ 0x7842000 16 0>,
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<DCC_READ 0x7842500 2 0>;
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};
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link_list_2 {
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qcom,curr-link-list = <3>;
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qcom,data-sink = "atb";
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qcom,link-list = <DCC_READ 0x18220d14 3 0>,
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<DCC_READ 0x18220d30 4 0>,
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<DCC_READ 0x18220d44 4 0>,
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<DCC_READ 0x18220d58 4 0>,
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<DCC_READ 0x18220fb4 3 0>,
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<DCC_READ 0x18220fd0 4 0>;
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};
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};
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