120 lines
4.2 KiB
Text
120 lines
4.2 KiB
Text
QTI Memlat Driver
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The QTI Memlat Driver monitors CPU performance counters to identify memory
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latency bound workloads and votes for DCVS HW (memory) frequencies based on
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the workload characteristics. This driver is a refactor of the arm-memlat-mon
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driver that was previously developed.
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Required structure:
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An instance of qcom-memlat must be described in three levels of device nodes.
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The first level describes the parent node. The second level describes a memlat
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group which manages voting for a particular DCVS HW device (e.g. DDR). The third
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level describes a memlat monitor ("mon") which comprises of a list of CPUs whose
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configured performance counters are used to vote for a DCVS HW frequency for the
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memlat group that it is part of.
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[First Level Nodes]
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Required properties:
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- compatible: Must be "qcom,memlat"
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Optional properties:
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- qcom,cyc-ev: The cycle count event that this driver monitors.
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Defaults to 0x11 if not specified.
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- qcom,inst-ev: The instruction count event that this driver monitors.
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Defaults to 0x08 if not specified.
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- qcom,stall-ev: The stall cycle event that this driver monitors.
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Assumes 100% stall if not specified.
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[Second Level Nodes]
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Required properties:
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- compatible: Must be "qcom,memlat-grp"
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- qcom,target-dev: A phandle to the QTI DCVS HW device node that this
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node will be using for voting.
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- qcom,miss-ev: The cache miss event that this memlat group uses to
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measure memory latency sensitivity to this DCVS HW.
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- qcom,sampling-path: A phandle to the QTI DCVS PATH device node that the
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memlat sampling algorithm will use for voting. This
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property or the qcom,threadlat-path property is
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required.
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- qcom,threadlat-path: A phandle to the QTI DCVS PATH device node that the
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threadlat algorithm will use for voting. This property
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or the qcom,sampling-path property is required.
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Optional properties:
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- qcom,access-ev: The cache access event that this driver optionally
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monitors to calculate writeback percentage.
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- qcom,wb-ev: The cache writeback event that this driver optionally
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monitors to calculate writeback percentage.
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[Third Level Nodes]
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Required properties:
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- compiatible: Must be "qcom,memlat-mon"
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- qcom,cpulist: List of CPU phandles to be monitored by this mon.
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- qcom,cpufreq-memfreq-tbl: A mapping table of cpu frequency to a memory
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(i.e. DCVS HW) frequency (both in units of kHz).
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A phandle that contains this property may be
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provided instead (to share tables across nodes).
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A phandle must be used in conjunction with the
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optional "qcom,ddr-type" property to support
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multiple DDR types.
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- qcom,sampling-enabled: Used to determine if this mon should be used by
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the memlat sampling algorithm. This property or
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the qcom,threadlat-enabled property is required.
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- qcom,threadlat-enabled: Used to determine if this mon should be used by
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the threadlat algorithm. This property or the
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qcom,sampling-enabled property is required.
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Optional properties:
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- qcom,compute-mon: Used to configure mon as a "compute" mon which
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means it monitors compute bound workloads.
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- qcom,ddr-type: Specifies the DDR type supported by the
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corresponding "qcom,cpufreq-memfreq-tbl" prop.
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Example:
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qcom_dcvs: qcom,dcvs {
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compatible = "qcom,dcvs";
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qcom_ddr_dcvs_hw: ddr {
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compatible = "qcom,dcvs-hw";
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ddr_dcvs_fp: fp {
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compatible = "qcom,dcvs-path";
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};
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};
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};
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silver_ddr_tbl: qcom,silver-ddr-tbl {
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ddr4-tbl {
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qcom,ddr-type = <7>;
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qcom,cpufreq-memfreq-tbl =
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< 300000 200000 >,
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< 691200 451000 >,
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< 1190400 547000 >,
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< 1459200 768000 >,
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< 1900800 1017000 >;
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};
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ddr5-tbl {
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qcom,ddr-type = <8>;
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qcom,cpufreq-memfreq-tbl =
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< 300000 200000 >,
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< 691200 451000 >,
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< 1190400 547000 >,
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< 1459200 768000 >,
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< 1900800 1555000 >;
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}
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};
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qcom_memlat: qcom,memlat {
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compatible = "qcom,memlat";
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memlat_ddr: ddr {
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compatible = "qcom,memlat-grp";
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qcom,target-dev = <&qcom_ddr_dcvs_hw>;
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qcom,sampling-path = <&ddr_dcvs_fp>;
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qcom,miss-ev = <0x1000>;
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silver_ddr_lat: silver {
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compatible = "qcom,memlat-mon";
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qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
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qcom,cpufreq-memfreq-tbl = <&silver_ddr_tbl>;
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qcom,sampling-enabled;
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};
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};
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};
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