90 lines
2.7 KiB
Text
90 lines
2.7 KiB
Text
Qualcomm Technologies, Inc. SPMI Debug Controller (PMIC Arbiter)
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The SPMI PMIC Arbiter is found on various QTI chips. It is an SPMI controller
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with wrapping arbitration logic to allow for multiple on-chip devices to control
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a single SPMI master.
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The PMIC Arbiter debug bus is present starting at arbiter version 5. It has
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read and write access to all PMIC peripherals regardless of ownership
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configurations. It cannot be used on production devices because it is disabled
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by an eFuse.
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See spmi.txt for the generic SPMI controller binding requirements for child
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nodes.
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Supported Properties:
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must be "qcom,spmi-pmic-arb-debug".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: List of address and size pairs. The address of the PMIC
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arbiter module is required. The address of the debug bus
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disabling fuse is optional.
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- reg-names
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Usage: required
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Value type: <stringlist>
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Definition: Address names. Must include "core" for the PMIC arbiter
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module and may include "fuse" for the debug bus disabling
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fuse. The strings must be specified in the same order as
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the corresponding addresses are specified in the reg
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property.
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- clocks
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: Clock tuple consisting of a phandle to a clock controller
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device and the clock ID number for the SPMI debug controller
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clock.
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- clock-names
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Usage: required if clocks property is specified
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Value type: <string>
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Definition: Defines the name of the clock defined in the "clocks"
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property. This must be "core_clk".
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- #address-cells
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Usage: required
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Value type: <u32>
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Definition: Must be 2.
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- #size-cells
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Usage: required
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Value type: <u32>
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Definition: Must be 0.
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- qcom,fuse-enable-bit
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Usage: optional
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Value type: <u32>
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Definition: The bit within the fuse register which is set when the debug
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bus is available. Only one of qcom,fuse-enable-bit and
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qcom,fuse-disable-bit should be specified if "fuse" is
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listed in the reg-names property.
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Supported values are 0 to 31.
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- qcom,fuse-disable-bit
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Usage: optional
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Value type: <u32>
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Definition: The bit within the fuse register which is set when the debug
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bus is not available. Only one of qcom,fuse-enable-bit and
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qcom,fuse-disable-bit should be specified if "fuse" is
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listed in the reg-names property.
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Supported values are 0 to 31.
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Example:
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qcom,spmi-debug@6b22000 {
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compatible = "qcom,spmi-pmic-arb-debug";
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reg = <0x6b22000 0x60>, <0x7820a8 4>;
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reg-names = "core", "fuse";
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clocks = <&clock_aop QDSS_CLK>;
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clock-names = "core_clk";
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qcom,fuse-disable-bit = <12>;
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#address-cells = <2>;
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#size-cells = <0>;
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};
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