85 lines
2.8 KiB
Text
85 lines
2.8 KiB
Text
Limits Management Hardware - DCVS
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The LMH-DCVS block is a hardware IP for every CPU cluster, to handle quick
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changes in thermal limits. The hardware responds to thermal variation amongst
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the CPUs in the cluster by requesting limits on the clock frequency and
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voltage on the OSM hardware.
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The LMH DCVS driver exports a virtual sensor that can be used to set the
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thermal limits on the hardware. LMH DCVS driver can be a platform CPU Cooling
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device, which registers with the CPU cooling device interface. All CPU device
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nodes should reference the corresponding LMH DCVS hardware in device tree.
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CPUs referencing the same LMH DCVS node will be associated with the
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corresponding cooling device as related CPUs.
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Properties:
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- compatible:
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Usage: required
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Value type: <string>
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Definition: shall be "qcom,msm-hw-limits"
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- interrupts:
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Usage: optional
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Value type: <interrupt_type interrupt_number interrupt_trigger_type>
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Definition: Should specify interrupt information about the debug
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interrupt generated by the LMH DCVSh hardware. LMH
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DCVSh hardware will generate this interrupt whenever
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it makes a new cpu DCVS decision.
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- qcom,affinity:
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Usage: optional
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Value type: <u32>
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Definition: Should specify the cluster affinity this hardware
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corresponds to.
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- isens_vref_1p8-supply:
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- isens_vref_0p8-supply:
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Usage: optional
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Value type: <phandle>
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Definition: Should specify the phandle of the vref regulator used by
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the isens hardware. This active only regulator will be
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enabled by LMH DCVSh. Isens hardware needs 1.8v and
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0.8v supply regulators.
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- isens-vref-1p8-settings:
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- isens-vref-0p8-settings:
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Usage: optional
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Value type: <u32 array>
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Definition: Should specify the min voltage(uV), max voltage(uV) and
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max load(uA) for the isens vref regulator. This
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property is valid only if there is valid entry for
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isens_vref_1p8-supply and isens_vref_0p8-supply.
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- reg:
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Usage: optional
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Value type: <a b>
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Definition: where 'a' is the starting register address of the OSM/LLM
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and 'b' is the size of OSM/LLM address space. The
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register space in index 0 should be LLM and index 1
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should be OSM.
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- qcom,no-cooling-device-register:
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Usage: optional
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Value type: <none>
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Definition: Should define this property if this driver doesn't need
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to register CPU cooling devices with thermal framework.
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Example:
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lmh_dcvs0: qcom,limits-dcvs@18350800 {
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compatible = "qcom,msm-hw-limits";
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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qcom,affinity = <0>;
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isens_vref_1p8-supply = <&pm8998_l1_ao>;
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isens-vref-1p8-settings = <880000 880000 36000>;
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isens_vref_0p8-supply = <&pm8998_l12_ao>;
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isens-vref-0p8-settings = <880000 880000 36000>;
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reg = <0x18350800 0x1000>, //LLM
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<0x18323000 0x1000>; //OSM
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};
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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qcom,lmh-dcvs = <&lmh_dcvs0>;;
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};
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