4147 lines
101 KiB
Text
4147 lines
101 KiB
Text
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
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#include <dt-bindings/clock/qcom,videocc-sm8250.h>
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#include <dt-bindings/clock/qcom,camcc-sm8250.h>
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#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
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#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
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#include <dt-bindings/clock/qcom,npucc-sm8250.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,kona.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/soc/qcom,dcc_v2.h>
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#include <dt-bindings/clock/qcom,aop-qmp.h>
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/ {
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model = "Qualcomm Technologies, Inc. kona";
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compatible = "qcom,kona";
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qcom,msm-id = <356 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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ddr-regions { };
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chosen {
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bootargs = "console=ttyMSM0,115200n8 loglevel=6 kpti=0 log_buf_len=256K kernel.panic_on_rcu_stall=1 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops fw_devlink.strict=1 cpufreq.default_governor=performance printk.console_no_auto_verbose=1 kasan=off pcie_ports=compat qcom_dma_heaps.enable_bitstream_contig_heap=y";
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};
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mem-offline {
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compatible = "qcom,mem-offline";
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offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
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<0x1 0xc0000000 0x0 0x80000000>,
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<0x2 0xc0000000 0x1 0x40000000>;
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granule = <512>;
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mboxes = <&qmp_aop 0>;
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ddr-old-version;
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};
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reserved_memory: reserved-memory { };
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aliases: aliases {
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ufshc1 = &ufshc_mem; /* Embedded UFS slot */
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serial0 = &qupv3_se12_2uart;
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hsuart0 = &qupv3_se6_4uart;
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hsuart1 = &qupv3_se13_4uart;
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pci-domain0 = &pcie0; /* PCIe0 domain */
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pci-domain1 = &pcie1; /* PCIe1 domain */
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pci-domain2 = &pcie2; /* PCIe2 domain */
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mmc1 = &sdhc_2; /* SDC2 SD card slot */
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usb0 = &dwc0; /*usb0 child node*/
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usb1 = &dwc1; /*usb1 child node*/
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF>;
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_1>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_100: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_100: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF>;
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power-domains = <&CPU_PD2>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_2>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_200: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_200: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF>;
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power-domains = <&CPU_PD3>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_3>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_300: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_300: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF>;
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power-domains = <&CPU_PD4>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_4>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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capacity-dmips-mhz = <1894>;
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dynamic-power-coefficient = <514>;
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#cooling-cells = <2>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_400: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_400: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF>;
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power-domains = <&CPU_PD5>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_5>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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capacity-dmips-mhz = <1894>;
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dynamic-power-coefficient = <514>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_500: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_500: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF>;
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power-domains = <&CPU_PD6>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_6>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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capacity-dmips-mhz = <1894>;
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dynamic-power-coefficient = <514>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_600: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_600: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF>;
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power-domains = <&CPU_PD7>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_7>;
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qcom,freq-domain = <&cpufreq_hw 2>;
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capacity-dmips-mhz = <1894>;
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dynamic-power-coefficient = <598>;
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#cooling-cells = <2>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_700: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_700: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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idle-states {
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entry-method = "psci";
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SILVER_OFF: silver-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <360>;
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exit-latency-us = <531>;
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min-residency-us = <3934>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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GOLD_OFF: gold-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <702>;
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exit-latency-us = <1061>;
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min-residency-us = <4488>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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APSS_OFF: cluster-e3 { /* LLCC off, AOSS sleep */
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compatible = "domain-idle-state";
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idle-state-name = "llcc-off";
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entry-latency-us = <3263>;
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exit-latency-us = <6562>;
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min-residency-us = <9987>;
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arm,psci-suspend-param = <0x4100c344>;
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};
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};
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soc: soc {
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: cpu-pd0 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD1: cpu-pd1 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD2: cpu-pd2 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD3: cpu-pd3 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD4: cpu-pd4 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD5: cpu-pd5 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD6: cpu-pd6 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD7: cpu-pd7 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CLUSTER_PD: cluster-pd {
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#power-domain-cells = <0>;
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domain-idle-states = <&APSS_OFF>;
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};
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};
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firmware: firmware {
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qcom_scm {
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compatible = "qcom,scm";
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qcom,dload-mode = <&tcsr 0x13000>;
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};
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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};
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qcom_smcinvoke {
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compatible = "qcom,smcinvoke";
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};
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android {
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compatible = "android,firmware";
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vbmeta {
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compatible = "android,vbmeta";
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parts = "vbmeta,boot,system,vendor,dtbo,recovery";
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};
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fstab {
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compatible = "android,fstab";
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vendor {
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compatible = "android,vendor";
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dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
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type = "ext4";
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mnt_flags = "ro,barrier=1,discard";
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fsmgr_flags = "wait,slotselect,avb";
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status = "ok";
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};
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};
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};
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};
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};
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&reserved_memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: hyp_region@80000000 {
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no-map;
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reg = <0x0 0x80000000 0x0 0x600000>;
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};
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xbl_aop_mem: xbl_aop_region@80700000 {
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no-map;
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reg = <0x0 0x80700000 0x0 0x160000>;
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};
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cmd_db: reserved-memory@80860000 {
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reg = <0x0 0x80860000 0x0 0x20000>;
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compatible = "qcom,cmd-db";
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no-map;
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};
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smem_mem: smem_region@80900000 {
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no-map;
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reg = <0x0 0x80900000 0x0 0x200000>;
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};
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removed_mem: removed_region@80b00000 {
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no-map;
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reg = <0x0 0x80b00000 0x0 0x5300000>;
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};
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pil_camera_mem: pil_camera_region@86200000 {
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no-map;
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reg = <0x0 0x86200000 0x0 0x500000>;
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};
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pil_wlan_fw_mem: pil_wlan_fw_region@86700000 {
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no-map;
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reg = <0x0 0x86700000 0x0 0x100000>;
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};
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pil_ipa_fw_mem: pil_ipa_fw_region@86800000 {
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no-map;
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reg = <0x0 0x86800000 0x0 0x10000>;
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};
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pil_ipa_gsi_mem: pil_ipa_gsi_region@86810000 {
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no-map;
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reg = <0x0 0x86810000 0x0 0xa000>;
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};
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pil_gpu_mem: pil_gpu_region@8681a000 {
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no-map;
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reg = <0x0 0x8681a000 0x0 0x2000>;
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};
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pil_npu_mem: pil_npu_region@86900000 {
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no-map;
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reg = <0x0 0x86900000 0x0 0x500000>;
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};
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|
|
video_mem: video_region@86e00000 {
|
|
no-map;
|
|
reg = <0x0 0x86e00000 0x0 0x500000>;
|
|
};
|
|
|
|
pil_cvp_mem: pil_cvp_region@87300000 {
|
|
no-map;
|
|
reg = <0x0 0x87300000 0x0 0x500000>;
|
|
};
|
|
|
|
rproc_cdsp_mem: rproc_cdsp_region@87800000 {
|
|
no-map;
|
|
reg = <0x0 0x87800000 0x0 0x1400000>;
|
|
};
|
|
|
|
rproc_slpi_mem: rproc_slpi_region@88c00000 {
|
|
no-map;
|
|
reg = <0x0 0x88c00000 0x0 0x1500000>;
|
|
};
|
|
|
|
rproc_adsp_mem: rproc_adsp_region@8a100000 {
|
|
no-map;
|
|
reg = <0x0 0x8a100000 0x0 0x1d00000>;
|
|
};
|
|
|
|
rproc_spss_mem: rproc_spss_region@8be00000 {
|
|
no-map;
|
|
reg = <0x0 0x8be00000 0x0 0x100000>;
|
|
};
|
|
|
|
cdsp_secure_heap: cdsp_secure_heap@8bf00000 {
|
|
no-map;
|
|
reg = <0x0 0x8bf00000 0x0 0x4600000>;
|
|
};
|
|
|
|
adsp_mem: adsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0xC00000>;
|
|
};
|
|
|
|
sdsp_mem: sdsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x800000>;
|
|
};
|
|
|
|
cdsp_mem: cdsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x400000>;
|
|
};
|
|
|
|
dfps_data_memory: dfps_data_region@9e300000 {
|
|
reg = <0x0 0x9e300000 0x0 0x0100000>;
|
|
label = "dfps_data_region";
|
|
};
|
|
|
|
dump_mem: mem_dump_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
size = <0 0x2800000>;
|
|
};
|
|
|
|
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x1000000>;
|
|
};
|
|
|
|
user_contig_mem: user_contig_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x1000000>;
|
|
};
|
|
|
|
qseecom_mem: qseecom_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x1400000>;
|
|
};
|
|
|
|
qseecom_ta_mem: qseecom_ta_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x1000000>;
|
|
};
|
|
|
|
secure_display_memory: secure_display_region { /* Secure UI */
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0xA400000>;
|
|
};
|
|
|
|
cnss_wlan_mem: cnss_wlan_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x1400000>;
|
|
};
|
|
|
|
/* global autoconfigured region for contiguous allocations */
|
|
system_cma:linux,cma {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x2000000>;
|
|
linux,cma-default;
|
|
};
|
|
|
|
mailbox_mem: mailbox_region {
|
|
compatible = "shared-dma-pool";
|
|
no-map;
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x20000>;
|
|
};
|
|
|
|
vendor: vendor {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
};
|
|
|
|
};
|
|
|
|
&soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
|
|
thermal_zones: thermal-zones {
|
|
};
|
|
|
|
|
|
slimbam: bamdma@3a84000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
qcom,controlled-remotely;
|
|
reg = <0x3a84000 0x2c000>;
|
|
num-channels = <31>;
|
|
interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
qcom,ee = <1>;
|
|
qcom,num-ees = <2>;
|
|
iommus = <&apps_smmu 0x1826 0x0>,
|
|
<&apps_smmu 0x182f 0x0>,
|
|
<&apps_smmu 0x1830 0x1>;
|
|
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
|
|
qcom,iommu-dma = "atomic";
|
|
};
|
|
|
|
slim_msm: slim@3ac0000 {
|
|
compatible = "qcom,slim-ngd-v1.5.0";
|
|
reg = <0x3ac0000 0x2c000>;
|
|
reg-names = "ctrl";
|
|
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,apps-ch-pipes = <0x700000>;
|
|
qcom,ea-pc = <0x2d0>;
|
|
iommus = <&apps_smmu 0x1826 0x0>,
|
|
<&apps_smmu 0x182f 0x0>,
|
|
<&apps_smmu 0x1830 0x1>;
|
|
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
|
|
qcom,iommu-dma = "atomic";
|
|
dmas = <&slimbam 3>, <&slimbam 4>;
|
|
dma-names = "rx", "tx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
intc: interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
reg = <0x17a00000 0x10000>, /* GICD */
|
|
<0x17a60000 0x100000>; /* GICR * 8 */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
arch_timer: timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
memtimer: timer@17c20000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17c20000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@17c21000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c21000 0x1000>,
|
|
<0x17c22000 0x1000>;
|
|
};
|
|
|
|
frame@17c23000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c23000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c25000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c25000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c27000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c27000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c29000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c29000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c2b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c2d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qcom_cedev: qcedev@1de0000 {
|
|
compatible = "qcom,qcedev";
|
|
reg = <0x1de0000 0x20000>,
|
|
<0x1dc4000 0x24000>;
|
|
reg-names = "crypto-base","crypto-bam-base";
|
|
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,bam-pipe-pair = <3>;
|
|
qcom,ce-hw-instance = <0>;
|
|
qcom,ce-device = <0>;
|
|
qcom,ce-hw-shared;
|
|
qcom,bam-ee = <0>;
|
|
qcom,smmu-s1-enable;
|
|
interconnect-names = "data_path";
|
|
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
|
|
qcom,no-clock-support;
|
|
iommus = <&apps_smmu 0x0586 0x0011>,
|
|
<&apps_smmu 0x0596 0x0011>;
|
|
qcom,iommu-dma = "atomic";
|
|
|
|
qcom_cedev_ns_cb {
|
|
compatible = "qcom,qcedev,context-bank";
|
|
label = "ns_context";
|
|
iommus = <&apps_smmu 0x592 0>,
|
|
<&apps_smmu 0x598 0>,
|
|
<&apps_smmu 0x599 0>,
|
|
<&apps_smmu 0x59F 0>;
|
|
};
|
|
|
|
qcom_cedev_s_cb {
|
|
compatible = "qcom,qcedev,context-bank";
|
|
label = "secure_context";
|
|
iommus = <&apps_smmu 0x593 0>,
|
|
<&apps_smmu 0x59C 0>,
|
|
<&apps_smmu 0x59D 0>,
|
|
<&apps_smmu 0x59E 0>;
|
|
qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
|
|
qcom,secure-context-bank;
|
|
};
|
|
};
|
|
|
|
qcom_qseecom: qseecom@82400000 {
|
|
compatible = "qcom,qseecom";
|
|
reg = <0x82400000 0x3A00000>;
|
|
reg-names = "secapp-region";
|
|
memory-region = <&qseecom_mem>;
|
|
qseecom_mem = <&qseecom_mem>;
|
|
qseecom_ta_mem = <&qseecom_ta_mem>;
|
|
user_contig_mem = <&user_contig_mem>;
|
|
qcom,hlos-num-ce-hw-instances = <1>;
|
|
qcom,hlos-ce-hw-instance = <0>;
|
|
qcom,qsee-ce-hw-instance = <0>;
|
|
qcom,disk-encrypt-pipe-pair = <2>;
|
|
qcom,support-fde;
|
|
qcom,no-clock-support;
|
|
qcom,fde-key-size;
|
|
qcom,appsbl-qseecom-support;
|
|
qcom,commonlib64-loaded-by-uefi;
|
|
qcom,qsee-reentrancy-support = <2>;
|
|
};
|
|
|
|
qcom_tzlog: tz-log@146bf720 {
|
|
compatible = "qcom,tz-log";
|
|
reg = <0x146bf720 0x3000>;
|
|
qcom,hyplog-enabled;
|
|
hyplog-address-offset = <0x410>;
|
|
hyplog-size-offset = <0x414>;
|
|
};
|
|
|
|
qcom_rng: qrng@793000 {
|
|
compatible = "qcom,msm-rng";
|
|
reg = <0x793000 0x1000>;
|
|
qcom,no-qrng-config;
|
|
qcom,no-clock-support;
|
|
};
|
|
|
|
cpu_pmu: cpu-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
qcom,irq-is-percpu;
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
spmi_bus: qcom,spmi@c440000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc440000 0x1100>,
|
|
<0xc600000 0x2000000>,
|
|
<0xe600000 0x100000>,
|
|
<0xe700000 0xa0000>,
|
|
<0xc40a000 0x26000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
cell-index = <0>;
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x18200000 0x10000>,
|
|
<0x18210000 0x10000>,
|
|
<0x18220000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
qcom,drv-count = <3>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
|
|
apps_rsc_drv2: drv@2 {
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
channel@0 {
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>,
|
|
<CONTROL_TCS 0>,
|
|
<FAST_PATH_TCS 0>;
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sm8250-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
apps_bcm_voter: bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
};
|
|
};
|
|
|
|
disp_rsc: rsc@af20000 {
|
|
label = "disp_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xaf20000 0x10000>;
|
|
reg-names = "drv-0";
|
|
qcom,drv-count = <1>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
|
|
|
|
disp_rsc_drv0: drv@0 {
|
|
qcom,drv-id = <0>;
|
|
qcom,tcs-offset = <0x1c00>;
|
|
channel@0 {
|
|
qcom,tcs-config = <ACTIVE_TCS 0>,
|
|
<SLEEP_TCS 1>,
|
|
<WAKE_TCS 1>,
|
|
<CONTROL_TCS 0>,
|
|
<FAST_PATH_TCS 0>;
|
|
};
|
|
|
|
disp_bcm_voter: bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,pdc", "qcom,kona-pdc";
|
|
reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
|
|
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
vendor_hooks: qcom,cpu-vendor-hooks {
|
|
compatible = "qcom,cpu-vendor-hooks";
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo-board {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <38400000>;
|
|
clock-output-names = "xo_board";
|
|
};
|
|
|
|
sleep_clk: sleep-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "sleep_clk";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
usb3_uni_phy_sec_gcc_usb30_pipe_clk: usb3-uni-phy-sec-gcc-usb30-pipe-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,gcc-sm8250", "syscon";
|
|
reg = <0x100000 0x1f0000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
|
|
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&pcie_0_pipe_clk>,
|
|
<&pcie_1_pipe_clk>,
|
|
<&pcie_2_pipe_clk>,
|
|
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
|
|
<&usb3_uni_phy_sec_gcc_usb30_pipe_clk>,
|
|
<&sleep_clk>;
|
|
clock-names = "bi_tcxo",
|
|
"bi_tcxo_ao",
|
|
"pcie_0_pipe_clk",
|
|
"pcie_1_pipe_clk",
|
|
"pcie_2_pipe_clk",
|
|
"usb3_phy_wrapper_gcc_usb30_pipe_clk",
|
|
"usb3_uni_phy_sec_gcc_usb30_pipe_clk",
|
|
"sleep_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
npucc: clock-controller@9800000 {
|
|
compatible = "qcom,sm8250-npucc", "syscon";
|
|
reg = <0x9800000 0x190000>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>,
|
|
<&gcc GCC_NPU_GPLL0_CLK_SRC>;
|
|
clock-names = "bi_tcxo",
|
|
"gcc_npu_gpll0_div_clk",
|
|
"gcc_npu_gpll0_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
videocc: clock-controller@abf0000 {
|
|
compatible = "qcom,sm8250-videocc", "syscon";
|
|
reg = <0xabf0000 0x10000>;
|
|
reg-names = "cc_base";
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
|
clock-names = "cfg_ahb_clk",
|
|
"bi_tcxo_ao",
|
|
"bi_tcxo",
|
|
"sleep_clk";
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&sleep_clk>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
camcc: clock-controller@ad00000 {
|
|
compatible = "qcom,sm8250-camcc", "syscon";
|
|
reg = <0xad00000 0x10000>;
|
|
reg-names = "cc_base";
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
|
clock-names = "cfg_ahb_clk",
|
|
"bi_tcxo",
|
|
"bi_tcxo_ao",
|
|
"sleep_clk";
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,sm8250-dispcc", "syscon";
|
|
reg = <0xaf00000 0x20000>;
|
|
reg-names = "cc_base";
|
|
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
|
clock-names = "cfg_ahb_clk",
|
|
"bi_tcxo",
|
|
"bi_tcxo_ao";
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpucc: clock-controller@3d90000 {
|
|
compatible = "qcom,sm8250-gpucc", "syscon";
|
|
reg = <0x3d90000 0x9000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
|
|
<&gcc GCC_GPU_GPLL0_CLK_SRC>;
|
|
clock-names = "bi_tcxo",
|
|
"gcc_gpu_gpll0_div_clk_src",
|
|
"gcc_gpu_gpll0_clk_src";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
apsscc: syscon@182a0000 {
|
|
compatible = "syscon";
|
|
reg = <0x182a0000 0x1c>;
|
|
};
|
|
|
|
mccc: syscon@90ba000 {
|
|
compatible = "syscon";
|
|
reg = <0x90ba000 0x54>;
|
|
};
|
|
|
|
debugcc: clock-controller@0 {
|
|
compatible = "qcom,sm8250-debugcc";
|
|
qcom,apsscc = <&apsscc>;
|
|
qcom,camcc = <&camcc>;
|
|
qcom,dispcc = <&dispcc>;
|
|
qcom,gcc = <&gcc>;
|
|
qcom,gpucc = <&gpucc>;
|
|
qcom,npucc = <&npucc>;
|
|
qcom,videocc = <&videocc>;
|
|
qcom,mccc = <&mccc>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&camcc 0>,
|
|
<&dispcc 0>,
|
|
<&gcc 0>,
|
|
<&gpucc 0>,
|
|
<&npucc 0>,
|
|
<&videocc 0>;
|
|
clock-names = "xo_clk_src",
|
|
"camcc",
|
|
"dispcc",
|
|
"gcc",
|
|
"gpucc",
|
|
"npucc",
|
|
"videocc";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
aggre1_noc: interconnect@16E0000 {
|
|
reg = <0x16E0000 0x1F180>;
|
|
compatible = "qcom,kona-aggre1_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
|
|
};
|
|
|
|
aggre2_noc: interconnect@1700000 {
|
|
reg = <0x1700000 0x3D180>;
|
|
compatible = "qcom,kona-aggre2_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
config_noc: interconnect@1500000 {
|
|
reg = <0x1500000 0x28000>;
|
|
compatible = "qcom,kona-config_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
dc_noc: interconnect@90C0000 {
|
|
reg = <0x90C0000 0x4200>;
|
|
compatible = "qcom,kona-dc_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
ipa_virt: interconnect@1 {
|
|
compatible = "qcom,kona-ipa_virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mc_virt: interconnect@2 {
|
|
compatible = "qcom,kona-mc_virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos", "disp";
|
|
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
|
};
|
|
|
|
gem_noc: interconnect@9100000 {
|
|
reg = <0x9100000 0xB4000>;
|
|
compatible = "qcom,kona-gem_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos", "disp";
|
|
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
|
};
|
|
|
|
mmss_noc: interconnect@1740000 {
|
|
reg = <0x1740000 0x1f080>;
|
|
compatible = "qcom,kona-mmss_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos", "disp";
|
|
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
|
};
|
|
|
|
system_noc: interconnect@1620000 {
|
|
reg = <0x1620000 0x1C200>;
|
|
compatible = "qcom,kona-system_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
compute_noc: interconnect@3 {
|
|
compatible = "qcom,kona-compute_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
npu_noc: interconnect@9990000 {
|
|
reg = <0x9990000 0x1600>;
|
|
compatible = "qcom,kona-npu_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
pcie_0_pipe_clk: pcie_0_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_1_pipe_clk: pcie_1_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_1_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_2_pipe_clk: pcie_2_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_2_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
/* GCC GDSCs */
|
|
pcie_0_gdsc: qcom,gdsc@16b004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x16b004 0x4>;
|
|
regulator-name = "pcie_0_gdsc";
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
pcie_1_gdsc: qcom,gdsc@18d004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x18d004 0x4>;
|
|
regulator-name = "pcie_1_gdsc";
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
pcie_2_gdsc: qcom,gdsc@106004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x106004 0x4>;
|
|
regulator-name = "pcie_2_gdsc";
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
ufs_phy_gdsc: qcom,gdsc@177004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x177004 0x4>;
|
|
regulator-name = "ufs_phy_gdsc";
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
usb30_prim_gdsc: qcom,gdsc@10f004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x10f004 0x4>;
|
|
regulator-name = "usb30_prim_gdsc";
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
usb30_sec_gdsc: qcom,gdsc@110004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x110004 0x4>;
|
|
regulator-name = "usb30_sec_gdsc";
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x17d050 0x4>;
|
|
regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <500>;
|
|
};
|
|
|
|
hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x17d058 0x4>;
|
|
regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <500>;
|
|
};
|
|
|
|
hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x17d054 0x4>;
|
|
regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <500>;
|
|
};
|
|
|
|
hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x17d06c 0x4>;
|
|
regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc";
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <500>;
|
|
};
|
|
|
|
/* CAM_CC GDSCs */
|
|
bps_gdsc: qcom,gdsc@ad07004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad07004 0x4>;
|
|
regulator-name = "bps_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
ife_0_gdsc: qcom,gdsc@ad0a004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad0a004 0x4>;
|
|
regulator-name = "ife_0_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
ife_1_gdsc: qcom,gdsc@ad0b004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad0b004 0x4>;
|
|
regulator-name = "ife_1_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
ipe_0_gdsc: qcom,gdsc@ad08004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad08004 0x4>;
|
|
regulator-name = "ipe_0_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
sbi_gdsc: qcom,gdsc@ad09004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad09004 0x4>;
|
|
regulator-name = "sbi_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
titan_top_gdsc: qcom,gdsc@ad0c144 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad0c144 0x4>;
|
|
regulator-name = "titan_top_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,gds-timeout = <500>;
|
|
};
|
|
|
|
/* DISP_CC GDSC */
|
|
mdss_core_gdsc: qcom,gdsc@af03000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaf03000 0x4>;
|
|
regulator-name = "mdss_core_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
proxy-supply = <&mdss_core_gdsc>;
|
|
qcom,proxy-consumer-enable;
|
|
};
|
|
|
|
/* GPU_CC GDSCs */
|
|
gpu_cx_hw_ctrl: syscon@3d91540 {
|
|
compatible = "syscon";
|
|
reg = <0x3d91540 0x4>;
|
|
};
|
|
|
|
gpu_cx_gdsc: qcom,gdsc@3d9106c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x3d9106c 0x4>;
|
|
regulator-name = "gpu_cx_gdsc";
|
|
hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,clk-dis-wait-val = <8>;
|
|
qcom,gds-timeout = <500>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
gpu_gx_domain_addr: syscon@3d91508 {
|
|
compatible = "syscon";
|
|
reg = <0x3d91508 0x4>;
|
|
};
|
|
|
|
gpu_gx_sw_reset: syscon@3d91008 {
|
|
compatible = "syscon";
|
|
reg = <0x3d91008 0x4>;
|
|
};
|
|
|
|
gpu_gx_gdsc: qcom,gdsc@3d9100c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x3d9100c 0x4>;
|
|
regulator-name = "gpu_gx_gdsc";
|
|
domain-addr = <&gpu_gx_domain_addr>;
|
|
sw-reset = <&gpu_gx_sw_reset>;
|
|
parent-supply = <&VDD_GFX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_GFX_LEVEL>;
|
|
qcom,skip-disable-before-sw-enable;
|
|
qcom,reset-aon-logic;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
/* NPU GDSC */
|
|
npu_core_gdsc: qcom,gdsc@9981004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x9981004 0x4>;
|
|
regulator-name = "npu_core_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&gcc GCC_NPU_CFG_AHB_CLK>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
qcom,sps {
|
|
compatible = "qcom,msm-sps-4k";
|
|
qcom,pipe-attr-ee;
|
|
};
|
|
|
|
/* VIDEO_CC GDSCs */
|
|
mvs0_gdsc: qcom,gdsc@abf0d18 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xabf0d18 0x4>;
|
|
regulator-name = "mvs0_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
mvs0c_gdsc: qcom,gdsc@abf0bf8 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xabf0bf8 0x4>;
|
|
regulator-name = "mvs0c_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
mvs1_gdsc: qcom,gdsc@abf0d98 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xabf0d98 0x4>;
|
|
regulator-name = "mvs1_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
mvs1c_gdsc: qcom,gdsc@abf0c98 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xabf0c98 0x4>;
|
|
regulator-name = "mvs1c_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
cpufreq_hw: qcom,cpufreq-hw {
|
|
compatible = "qcom,cpufreq-epss";
|
|
reg = <0x18591000 0x1000>, <0x18592000 0x1000>,
|
|
<0x18593000 0x1000>;
|
|
reg-names = "freq-domain0", "freq-domain1",
|
|
"freq-domain2";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int";
|
|
#freq-domain-cells = <1>;
|
|
|
|
cpu7_notify: cpu7-notify {
|
|
qcom,cooling-cpu = <&CPU7>;
|
|
#cooling-cells = <2>;
|
|
};
|
|
};
|
|
|
|
llcc_pmu: llcc-pmu@9095000 {
|
|
compatible = "qcom,llcc-pmu-ver2";
|
|
reg = <0x09095000 0x300>;
|
|
reg-names = "lagg-base";
|
|
};
|
|
|
|
qcom_pmu: qcom,pmu {
|
|
compatible = "qcom,pmu";
|
|
qcom,pmu-events-tbl =
|
|
< 0x0008 0xFF 0xFF 0xFF >,
|
|
< 0x0011 0xFF 0xFF 0xFF >,
|
|
< 0x0017 0xFF 0xFF 0xFF >,
|
|
< 0x002A 0xFF 0xFF 0xFF >;
|
|
};
|
|
|
|
ddr_freq_table: ddr-freq-table {
|
|
qcom,freq-tbl =
|
|
< 200000 >,
|
|
< 300000 >,
|
|
< 451000 >,
|
|
< 547000 >,
|
|
< 681000 >,
|
|
< 768000 >,
|
|
< 1017000 >,
|
|
< 1353000 >,
|
|
< 1555000 >,
|
|
< 1804000 >,
|
|
< 2092000 >,
|
|
< 2736000 >;
|
|
};
|
|
|
|
llcc_freq_table: llcc-freq-table {
|
|
qcom,freq-tbl =
|
|
< 150000 >,
|
|
< 300000 >,
|
|
< 466000 >,
|
|
< 600000 >,
|
|
< 806000 >,
|
|
< 933000 >,
|
|
< 1000000 >;
|
|
};
|
|
|
|
ddrqos_freq_table: ddrqos-freq-table {
|
|
qcom,freq-tbl =
|
|
< 0 >,
|
|
< 1 >;
|
|
};
|
|
|
|
qcom_dcvs: qcom,dcvs {
|
|
compatible = "qcom,dcvs";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
qcom_l3_dcvs_hw: l3 {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <2>;
|
|
qcom,bus-width = <32>;
|
|
reg = <0x18590000 0x4>, <0x18590100 0xa0>;
|
|
reg-names = "l3-base", "l3tbl-base";
|
|
|
|
l3_dcvs_sp: sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0>;
|
|
qcom,shared-offset = <0x0090>;
|
|
};
|
|
};
|
|
|
|
qcom_ddr_dcvs_hw: ddr {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <0>;
|
|
qcom,bus-width = <4>;
|
|
qcom,freq-tbl = <&ddr_freq_table>;
|
|
|
|
ddr_dcvs_sp: sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0>;
|
|
interconnects = <&mc_virt MASTER_LLCC
|
|
&mc_virt SLAVE_EBI1>;
|
|
};
|
|
};
|
|
|
|
qcom_llcc_dcvs_hw: llcc {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <1>;
|
|
qcom,bus-width = <16>;
|
|
qcom,freq-tbl = <&llcc_freq_table>;
|
|
|
|
llcc_dcvs_sp: sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0>;
|
|
interconnects = <&gem_noc MASTER_APPSS_PROC
|
|
&gem_noc SLAVE_LLCC>;
|
|
};
|
|
};
|
|
|
|
qcom_ddrqos_dcvs_hw: ddrqos {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <3>;
|
|
qcom,bus-width = <1>;
|
|
qcom,freq-tbl = <&ddrqos_freq_table>;
|
|
|
|
ddrqos_dcvs_sp: sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0>;
|
|
interconnects = <&mc_virt MASTER_LLCC
|
|
&mc_virt SLAVE_EBI1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom_memlat: qcom,memlat {
|
|
compatible = "qcom,memlat";
|
|
|
|
ddr {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
|
|
qcom,sampling-path = <&ddr_dcvs_sp>;
|
|
qcom,miss-ev = <0x2A>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
|
|
qcom,sampling-enabled;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 200000 >,
|
|
< 729600 451000 >,
|
|
< 1132800 547000 >,
|
|
< 1497600 768000 >,
|
|
< 1670400 1017000 >;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
|
qcom,sampling-enabled;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 200000 >,
|
|
< 691200 451000 >,
|
|
< 806400 547000 >,
|
|
< 1017600 768000 >,
|
|
< 1228800 1017000 >,
|
|
< 1804800 1555000 >,
|
|
< 2227200 1804000 >,
|
|
< 2380800 2092000 >,
|
|
< 2476800 2736000 >;
|
|
};
|
|
|
|
gold-compute {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
|
qcom,sampling-enabled;
|
|
qcom,compute-mon;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 1804800 200000 >,
|
|
< 2380800 1017000 >,
|
|
< 2500000 2736000 >;
|
|
};
|
|
};
|
|
|
|
llcc {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
|
|
qcom,sampling-path = <&llcc_dcvs_sp>;
|
|
qcom,miss-ev = <0x2A>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
|
|
qcom,sampling-enabled;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 150000 >,
|
|
< 729600 300000 >,
|
|
< 1497600 466000 >,
|
|
< 1670400 600000 >;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
|
qcom,sampling-enabled;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 150000 >,
|
|
< 691200 300000 >,
|
|
< 1017600 466000 >,
|
|
< 1228800 600000 >,
|
|
< 1804800 806000 >,
|
|
< 2227200 933000 >,
|
|
< 2476800 1000000 >;
|
|
};
|
|
};
|
|
|
|
l3 {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <&qcom_l3_dcvs_hw>;
|
|
qcom,sampling-path = <&l3_dcvs_sp>;
|
|
qcom,miss-ev = <0x17>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
|
|
qcom,sampling-enabled;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 300000 >,
|
|
< 403200 403200 >,
|
|
< 518400 518400 >,
|
|
< 633600 614400 >,
|
|
< 825600 729600 >,
|
|
< 921600 825600 >,
|
|
< 1036800 921600 >,
|
|
< 1132800 1036800 >,
|
|
< 1228800 1132800 >,
|
|
< 1401600 1228800 >,
|
|
< 1497600 1305600 >,
|
|
< 1670400 1382400 >;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
|
|
qcom,sampling-enabled;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 300000 >,
|
|
< 806400 614400 >,
|
|
< 1017600 729600 >,
|
|
< 1228800 921600 >,
|
|
< 1689600 1228800 >,
|
|
< 1804800 1305600 >,
|
|
< 2227200 1382400 >;
|
|
};
|
|
|
|
prime {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU7>;
|
|
qcom,sampling-enabled;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 300000 >,
|
|
< 806400 614400 >,
|
|
< 1017600 729600 >,
|
|
< 1228800 921600 >,
|
|
< 1689600 1228800 >,
|
|
< 1804800 1305600 >,
|
|
< 2227200 1382400 >;
|
|
};
|
|
};
|
|
|
|
ddrqos {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
|
|
qcom,sampling-path = <&ddrqos_dcvs_sp>;
|
|
qcom,miss-ev = <0x2A>;
|
|
|
|
ddrqos_gold_lat: gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
|
qcom,sampling-enabled;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 1 >,
|
|
< 3000000 2 >;
|
|
};
|
|
};
|
|
};
|
|
|
|
bwmon_llcc: qcom,bwmon-llcc@90b6400 {
|
|
compatible = "qcom,bwmon4";
|
|
reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
|
|
reg-names = "base", "global_base";
|
|
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,mport = <0>;
|
|
qcom,hw-timer-hz = <19200000>;
|
|
qcom,count-unit = <0x10000>;
|
|
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
|
|
};
|
|
|
|
bwmon_ddr: qcom,bwmon-ddr@9091000 {
|
|
compatible = "qcom,bwmon5";
|
|
reg = <0x9091000 0x1000>;
|
|
reg-names = "base";
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,hw-timer-hz = <19200000>;
|
|
qcom,count-unit = <0x10000>;
|
|
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
|
|
};
|
|
|
|
qcom,chd {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "core";
|
|
qcom,chd-percpu-info = <&CPU0 0x18000058 0x18000060>,
|
|
<&CPU1 0x18010058 0x18010060>,
|
|
<&CPU2 0x18020058 0x18020060>,
|
|
<&CPU3 0x18030058 0x18030060>,
|
|
<&CPU4 0x18040058 0x18040060>,
|
|
<&CPU5 0x18050058 0x18050060>,
|
|
<&CPU6 0x18060058 0x18060060>,
|
|
<&CPU7 0x18070058 0x18070060>;
|
|
};
|
|
|
|
dsu_pmu@0 {
|
|
compatible = "arm,dsu-pmu";
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
|
|
<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
|
|
};
|
|
|
|
ufsphy_mem: ufsphy_mem@1d87000 {
|
|
reg = <0x1d87000 0xe00>; /* PHY regs */
|
|
reg-names = "phy_mem";
|
|
#phy-cells = <0>;
|
|
|
|
lanes-per-direction = <2>;
|
|
|
|
clock-names = "ref_clk_src",
|
|
"ref_aux_clk";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
|
|
|
|
resets = <&ufshc_mem 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ufs_ice: ufsice@1d90000 {
|
|
compatible = "qcom,ice";
|
|
reg = <0x1d90000 0x8000>;
|
|
qcom,enable-ice-clk;
|
|
clock-names = "ufs_core_clk", "bus_clk",
|
|
"iface_clk", "ice_core_clk";
|
|
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_1X_CLKREF_EN>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
|
|
qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
|
|
vdd-hba-supply = <&ufs_phy_gdsc>;
|
|
qcom,bus-vector-names = "MIN",
|
|
"MAX";
|
|
qcom,instance-type = "ufs";
|
|
qcom,num-fde-slots = <31>;
|
|
};
|
|
|
|
ufshc_mem: ufshc@1d84000 {
|
|
compatible = "qcom,ufshc";
|
|
reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;
|
|
reg-names = "ufs_mem", "ufs_ice";
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&ufsphy_mem>;
|
|
phy-names = "ufsphy";
|
|
#reset-cells = <1>;
|
|
|
|
lanes-per-direction = <2>;
|
|
dev-ref-clk-freq = <0>; /* 19.2 MHz */
|
|
|
|
clock-names =
|
|
"core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"core_clk_ice",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk",
|
|
"rx_lane1_sync_clk";
|
|
clocks =
|
|
<&gcc GCC_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
|
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
|
freq-table-hz =
|
|
<37500000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<37500000 300000000>,
|
|
<37500000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
|
|
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
|
|
interconnect-names = "ufs-ddr", "cpu-ufs";
|
|
|
|
qcom,ufs-bus-bw,name = "ufshc_mem";
|
|
qcom,ufs-bus-bw,num-cases = <26>;
|
|
qcom,ufs-bus-bw,num-paths = <2>;
|
|
qcom,ufs-bus-bw,vectors-KBps =
|
|
/*
|
|
* During HS G3 UFS runs at nominal voltage corner, vote
|
|
* higher bandwidth to push other buses in the data path
|
|
* to run at nominal to achieve max throughput.
|
|
* 4GBps pushes BIMC to run at nominal.
|
|
* 200MBps pushes CNOC to run at nominal.
|
|
* Vote for half of this bandwidth for HS G3 1-lane.
|
|
* For max bandwidth, vote high enough to push the buses
|
|
* to run in turbo voltage corner.
|
|
*/
|
|
<0 0>, <0 0>, /* No vote */
|
|
<922 0>, <1000 0>, /* PWM G1 */
|
|
<1844 0>, <1000 0>, /* PWM G2 */
|
|
<3688 0>, <1000 0>, /* PWM G3 */
|
|
<7376 0>, <1000 0>, /* PWM G4 */
|
|
<1844 0>, <1000 0>, /* PWM G1 L2 */
|
|
<3688 0>, <1000 0>, /* PWM G2 L2 */
|
|
<7376 0>, <1000 0>, /* PWM G3 L2 */
|
|
<14752 0>, <1000 0>, /* PWM G4 L2 */
|
|
<127796 0>, <1000 0>, /* HS G1 RA */
|
|
<255591 0>, <1000 0>, /* HS G2 RA */
|
|
<2097152 0>, <102400 0>, /* HS G3 RA */
|
|
<4194304 0>, <204800 0>, /* HS G4 RA */
|
|
<255591 0>, <1000 0>, /* HS G1 RA L2 */
|
|
<511181 0>, <1000 0>, /* HS G2 RA L2 */
|
|
<4194304 0>, <204800 0>, /* HS G3 RA L2 */
|
|
<8388608 0>, <409600 0>, /* HS G4 RA L2 */
|
|
<149422 0>, <1000 0>, /* HS G1 RB */
|
|
<298189 0>, <1000 0>, /* HS G2 RB */
|
|
<2097152 0>, <102400 0>, /* HS G3 RB */
|
|
<4194304 0>, <204800 0>, /* HS G4 RB */
|
|
<298189 0>, <1000 0>, /* HS G1 RB L2 */
|
|
<596378 0>, <1000 0>, /* HS G2 RB L2 */
|
|
/* As UFS working in HS G3 RB L2 mode, aggregated
|
|
* bandwidth (AB) should take care of providing
|
|
* optimum throughput requested. However, as tested,
|
|
* in order to scale up CNOC clock, instantaneous
|
|
* bindwidth (IB) needs to be given a proper value too.
|
|
*/
|
|
<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
|
|
<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
|
|
<7643136 0>, <307200 0>; /* Max. bandwidth */
|
|
|
|
qcom,bus-vector-names = "MIN",
|
|
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
|
|
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
|
|
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
|
|
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
|
|
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
|
|
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
|
|
"MAX";
|
|
reset-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>;
|
|
|
|
resets = <&gcc GCC_UFS_PHY_BCR>;
|
|
reset-names = "rst";
|
|
iommus = <&apps_smmu 0xE0 0x0>;
|
|
qcom,iommu-dma = "bypass";
|
|
|
|
status = "disabled";
|
|
|
|
qos0 {
|
|
mask = <0x0f>;
|
|
vote = <44>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0xf0>;
|
|
vote = <44>;
|
|
};
|
|
};
|
|
|
|
qcom,rmtfs_sharedmem@0 {
|
|
compatible = "qcom,sharedmem-uio";
|
|
reg = <0x0 0x280000>;
|
|
reg-names = "rmtfs";
|
|
qcom,client-id = <0x00000001>;
|
|
};
|
|
|
|
sdhc2_opp_table: sdhc2-opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
opp-peak-kBps = <1600000 280000>;
|
|
opp-avg-kBps = <50000 0>;
|
|
};
|
|
|
|
opp-202000000 {
|
|
opp-hz = /bits/ 64 <202000000>;
|
|
opp-peak-kBps = <5600000 1500000>;
|
|
opp-avg-kBps = <104000 0>;
|
|
};
|
|
};
|
|
|
|
sdhc_2: sdhci@8804000 {
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x8804000 0x1000>;
|
|
reg-names = "hc";
|
|
|
|
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
|
|
bus-width = <4>;
|
|
no-sdio;
|
|
no-mmc;
|
|
qcom,restore-after-cx-collapse;
|
|
|
|
iommus = <&apps_smmu 0x4A0 0x0>;
|
|
qcom,iommu-dma = "fastmap";
|
|
dma-coherent;
|
|
|
|
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
|
|
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
|
|
interconnect-names = "sdhc-ddr","cpu-sdhc";
|
|
operating-points-v2 = <&sdhc2_opp_table>;
|
|
|
|
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
|
qcom,dll-hsr-list = <0x0007642C 0xA800 0x10
|
|
0x2C010800 0x80040868>;
|
|
|
|
status = "disabled";
|
|
|
|
qos0 {
|
|
mask = <0x3f>;
|
|
vote = <44>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0xc0>;
|
|
vote = <44>;
|
|
};
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
smem: qcom,smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_mem>;
|
|
depends-on-supply = <&tcsr_mutex>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
tcsr: syscon@1fc0000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fc0000 0x30000>;
|
|
};
|
|
|
|
cluster-device {
|
|
compatible = "qcom,lpm-cluster-dev";
|
|
power-domains = <&CLUSTER_PD>;
|
|
};
|
|
|
|
soc-sleep-stats@c3f0000 {
|
|
compatible = "qcom,rpmh-sleep-stats";
|
|
reg = <0xc3f0000 0x400>;
|
|
ss-name = "modem", "adsp", "adsp_island",
|
|
"cdsp", "apss";
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "aop";
|
|
};
|
|
|
|
subsystem-sleep-stats@c3f0000 {
|
|
compatible = "qcom,subsystem-sleep-stats";
|
|
reg = <0xc3f0000 0x400>;
|
|
};
|
|
|
|
ipcc_mproc: qcom,ipcc@408000 {
|
|
compatible = "qcom,ipcc";
|
|
reg = <0x408000 0x1000>;
|
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
aoss_qmp: power-controller@c300000 {
|
|
compatible = "qcom,kona-aoss-qmp";
|
|
reg = <0xc300000 0x400>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
#power-domain-cells = <1>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,qmp = <&aoss_qmp>;
|
|
label = "aop";
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
cache-controller@9200000 {
|
|
compatible = "qcom,kona-llcc";
|
|
reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
|
|
reg-names = "llcc_base", "llcc_broadcast_base";
|
|
cap-based-alloc-and-pwr-collapse;
|
|
|
|
llcc-perfmon {
|
|
compatible = "qcom,llcc-perfmon";
|
|
clocks = <&aoss_qmp QDSS_CLK>;
|
|
clock-names = "qdss_clk";
|
|
};
|
|
};
|
|
|
|
wdog: qcom,wdt@17c10000 {
|
|
compatible = "qcom,msm-watchdog";
|
|
reg = <0x17c10000 0x1000>;
|
|
reg-names = "wdt-base";
|
|
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,bark-time = <11000>;
|
|
qcom,pet-time = <9360>;
|
|
qcom,wakeup-enable;
|
|
qcom,ipi-ping;
|
|
};
|
|
|
|
qcom,mem-buf {
|
|
compatible = "qcom,mem-buf";
|
|
qcom,mem-buf-capabilities = "supplier";
|
|
qcom,vmid = <3>;
|
|
};
|
|
|
|
qcom,mem-buf-msgq {
|
|
compatible = "qcom,mem-buf-msgq";
|
|
};
|
|
|
|
qcom,msm-imem@146bf000 {
|
|
compatible = "qcom,msm-imem";
|
|
reg = <0x146bf000 0x1000>;
|
|
ranges = <0x0 0x146bf000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x8>;
|
|
};
|
|
|
|
restart_reason@65c {
|
|
compatible = "qcom,msm-imem-restart_reason";
|
|
reg = <0x65c 0x4>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x4>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0xc>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,pil-reloc-info";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
pil@6dc {
|
|
compatible = "qcom,msm-imem-pil-disable-timeout";
|
|
reg = <0x6dc 0x4>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
};
|
|
|
|
restart@c264000 {
|
|
compatible = "qcom,pshold";
|
|
reg = <0xc264000 0x4>, <0x1fd3000 0x4>;
|
|
reg-names = "pshold-base", "tcsr-boot-misc-detect";
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@c221000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0xc221000 0x1000>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
qcom-secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
};
|
|
|
|
mini_dump_mode {
|
|
compatible = "qcom,minidump";
|
|
status = "ok";
|
|
};
|
|
|
|
ssc_sensors: qcom,msm-ssc-sensors {
|
|
compatible = "qcom,msm-ssc-sensors";
|
|
status = "ok";
|
|
qcom,firmware-name = "slpi";
|
|
qcom,rproc-handle = <&slpi_pas>;
|
|
};
|
|
|
|
mem_dump {
|
|
compatible = "qcom,mem-dump";
|
|
memory-region = <&dump_mem>;
|
|
|
|
c0_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x0>;
|
|
};
|
|
|
|
c100_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x1>;
|
|
};
|
|
|
|
c200_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x2>;
|
|
};
|
|
|
|
c300_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x3>;
|
|
};
|
|
|
|
c400_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x4>;
|
|
};
|
|
|
|
c500_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x5>;
|
|
};
|
|
|
|
c600_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x6>;
|
|
};
|
|
|
|
c700_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x7>;
|
|
};
|
|
|
|
c0_scandump {
|
|
qcom,dump-size = <0x10100>;
|
|
qcom,dump-id = <0x130>;
|
|
};
|
|
|
|
c100_scandump {
|
|
qcom,dump-size = <0x10100>;
|
|
qcom,dump-id = <0x131>;
|
|
};
|
|
|
|
c200_scandump {
|
|
qcom,dump-size = <0x10100>;
|
|
qcom,dump-id = <0x132>;
|
|
};
|
|
|
|
c300_scandump {
|
|
qcom,dump-size = <0x10100>;
|
|
qcom,dump-id = <0x133>;
|
|
};
|
|
|
|
c400_scandump {
|
|
qcom,dump-size = <0x1a4c0>;
|
|
qcom,dump-id = <0x134>;
|
|
};
|
|
|
|
c500_scandump {
|
|
qcom,dump-size = <0x1a4c0>;
|
|
qcom,dump-id = <0x135>;
|
|
};
|
|
|
|
c600_scandump {
|
|
qcom,dump-size = <0x1a4c0>;
|
|
qcom,dump-id = <0x136>;
|
|
};
|
|
|
|
c700_scandump {
|
|
qcom,dump-size = <0x1a4c0>;
|
|
qcom,dump-id = <0x137>;
|
|
};
|
|
|
|
cpuss_reg {
|
|
qcom,dump-size = <0x30000>;
|
|
qcom,dump-id = <0xef>;
|
|
};
|
|
|
|
l1_icache0 {
|
|
qcom,dump-size = <0x10800>;
|
|
qcom,dump-id = <0x60>;
|
|
};
|
|
|
|
l1_icache100 {
|
|
qcom,dump-size = <0x10800>;
|
|
qcom,dump-id = <0x61>;
|
|
};
|
|
|
|
l1_icache200 {
|
|
qcom,dump-size = <0x10800>;
|
|
qcom,dump-id = <0x62>;
|
|
};
|
|
|
|
l1_icache300 {
|
|
qcom,dump-size = <0x10800>;
|
|
qcom,dump-id = <0x63>;
|
|
};
|
|
|
|
l1_icache400 {
|
|
qcom,dump-size = <0x26000>;
|
|
qcom,dump-id = <0x64>;
|
|
};
|
|
|
|
l1_icache500 {
|
|
qcom,dump-size = <0x26000>;
|
|
qcom,dump-id = <0x65>;
|
|
};
|
|
|
|
l1_icache600 {
|
|
qcom,dump-size = <0x26000>;
|
|
qcom,dump-id = <0x66>;
|
|
};
|
|
|
|
l1_icache700 {
|
|
qcom,dump-size = <0x26000>;
|
|
qcom,dump-id = <0x67>;
|
|
};
|
|
|
|
l1_dcache0 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x80>;
|
|
};
|
|
|
|
l1_dcache100 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x81>;
|
|
};
|
|
|
|
l1_dcache200 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x82>;
|
|
};
|
|
|
|
l1_dcache300 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x83>;
|
|
};
|
|
|
|
l1_dcache400 {
|
|
qcom,dump-size = <0x1A000>;
|
|
qcom,dump-id = <0x84>;
|
|
};
|
|
|
|
l1_dcache500 {
|
|
qcom,dump-size = <0x1A000>;
|
|
qcom,dump-id = <0x85>;
|
|
};
|
|
|
|
l1_dcache600 {
|
|
qcom,dump-size = <0x1A000>;
|
|
qcom,dump-id = <0x86>;
|
|
};
|
|
|
|
l1_dcache700 {
|
|
qcom,dump-size = <0x1A000>;
|
|
qcom,dump-id = <0x87>;
|
|
};
|
|
|
|
l1_itlb400 {
|
|
qcom,dump-size = <0x300>;
|
|
qcom,dump-id = <0x24>;
|
|
};
|
|
|
|
l1_itlb500 {
|
|
qcom,dump-size = <0x300>;
|
|
qcom,dump-id = <0x25>;
|
|
};
|
|
|
|
l1_itlb600 {
|
|
qcom,dump-size = <0x300>;
|
|
qcom,dump-id = <0x26>;
|
|
};
|
|
|
|
l1_itlb700 {
|
|
qcom,dump-size = <0x300>;
|
|
qcom,dump-id = <0x27>;
|
|
};
|
|
|
|
l1_dtlb400 {
|
|
qcom,dump-size = <0x480>;
|
|
qcom,dump-id = <0x44>;
|
|
};
|
|
|
|
l1_dtlb500 {
|
|
qcom,dump-size = <0x480>;
|
|
qcom,dump-id = <0x45>;
|
|
};
|
|
|
|
l1_dtlb600 {
|
|
qcom,dump-size = <0x480>;
|
|
qcom,dump-id = <0x46>;
|
|
};
|
|
|
|
l1_dtlb700 {
|
|
qcom,dump-size = <0x480>;
|
|
qcom,dump-id = <0x47>;
|
|
};
|
|
|
|
l2_cache400 {
|
|
qcom,dump-size = <0x68000>;
|
|
qcom,dump-id = <0xc4>;
|
|
};
|
|
|
|
l2_cache500 {
|
|
qcom,dump-size = <0x68000>;
|
|
qcom,dump-id = <0xc5>;
|
|
};
|
|
|
|
l2_cache600 {
|
|
qcom,dump-size = <0x68000>;
|
|
qcom,dump-id = <0xc6>;
|
|
};
|
|
|
|
l2_cache700 {
|
|
qcom,dump-size = <0xD0000>;
|
|
qcom,dump-id = <0xc7>;
|
|
};
|
|
|
|
l2_tlb0 {
|
|
qcom,dump-size = <0x6000>;
|
|
qcom,dump-id = <0x120>;
|
|
};
|
|
|
|
l2_tlb100 {
|
|
qcom,dump-size = <0x6000>;
|
|
qcom,dump-id = <0x121>;
|
|
};
|
|
|
|
l2_tlb200 {
|
|
qcom,dump-size = <0x6000>;
|
|
qcom,dump-id = <0x122>;
|
|
};
|
|
|
|
l2_tlb300 {
|
|
qcom,dump-size = <0x6000>;
|
|
qcom,dump-id = <0x123>;
|
|
};
|
|
|
|
l2_tlb400 {
|
|
qcom,dump-size = <0x7800>;
|
|
qcom,dump-id = <0x124>;
|
|
};
|
|
|
|
l2_tlb500 {
|
|
qcom,dump-size = <0x7800>;
|
|
qcom,dump-id = <0x125>;
|
|
};
|
|
|
|
l2_tlb600 {
|
|
qcom,dump-size = <0x7800>;
|
|
qcom,dump-id = <0x126>;
|
|
};
|
|
|
|
l2_tlb700 {
|
|
qcom,dump-size = <0x7800>;
|
|
qcom,dump-id = <0x127>;
|
|
};
|
|
|
|
gemnoc {
|
|
qcom,dump-size = <0x100000>;
|
|
qcom,dump-id = <0x162>;
|
|
};
|
|
|
|
mhm_scan {
|
|
qcom,dump-size = <0x20000>;
|
|
qcom,dump-id = <0x161>;
|
|
};
|
|
|
|
rpmh {
|
|
qcom,dump-size = <0x2000000>;
|
|
qcom,dump-id = <0xec>;
|
|
};
|
|
|
|
rpm_sw {
|
|
qcom,dump-size = <0x28000>;
|
|
qcom,dump-id = <0xea>;
|
|
};
|
|
|
|
pmic {
|
|
qcom,dump-size = <0x80000>;
|
|
qcom,dump-id = <0xe4>;
|
|
};
|
|
|
|
fcm {
|
|
qcom,dump-size = <0x8400>;
|
|
qcom,dump-id = <0xee>;
|
|
};
|
|
|
|
etf_swao {
|
|
qcom,dump-size = <0x10000>;
|
|
qcom,dump-id = <0xf1>;
|
|
};
|
|
|
|
etr_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x100>;
|
|
};
|
|
|
|
etfswao_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x102>;
|
|
};
|
|
|
|
misc_data {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0xe8>;
|
|
};
|
|
|
|
etf_slpi {
|
|
qcom,dump-size = <0x4000>;
|
|
qcom,dump-id = <0xf3>;
|
|
};
|
|
|
|
etfslpi_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x103>;
|
|
};
|
|
|
|
etf_lpass {
|
|
qcom,dump-size = <0x4000>;
|
|
qcom,dump-id = <0xf4>;
|
|
};
|
|
|
|
etflpass_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x104>;
|
|
};
|
|
};
|
|
|
|
eud: qcom,msm-eud@88e0000 {
|
|
compatible = "qcom,msm-eud";
|
|
interrupt-names = "eud_irq";
|
|
interrupt-parent = <&pdc>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x088E0000 0x2000>,
|
|
<0x088E2000 0x1000>;
|
|
reg-names = "eud_base", "eud_mode_mgr2";
|
|
qcom,secure-eud-en;
|
|
qcom,eud-clock-vote-req;
|
|
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_BCR>;
|
|
clock-names = "eud_ahb2phy_clk";
|
|
};
|
|
|
|
adsp_pas: remoteproc-adsp@17300000 {
|
|
compatible = "qcom,kona-adsp-pas";
|
|
reg = <0x17300000 0x00100>;
|
|
status = "ok";
|
|
|
|
cx-supply = <&L11A_LEVEL>;
|
|
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
mx-supply = <&L4A_LEVEL>;
|
|
mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
reg-names = "cx", "mx";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
qcom,signal-aop;
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
memory-region = <&rproc_adsp_mem>;
|
|
|
|
/* Inputs from ssc */
|
|
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 0 0>,
|
|
<&adsp_smp2p_in 2 0>,
|
|
<&adsp_smp2p_in 1 0>,
|
|
<&adsp_smp2p_in 3 0>,
|
|
<&adsp_smp2p_in 7 0>;
|
|
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"handover",
|
|
"ready",
|
|
"stop-ack",
|
|
"shutdown-ack";
|
|
|
|
/* Outputs to turing */
|
|
qcom,smem-states = <&adsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
glink_edge: glink-edge {
|
|
qcom,remote-pid = <2>;
|
|
transport = "smem";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "adsp_smem";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "adsp";
|
|
qcom,glink-label = "lpass";
|
|
|
|
qcom,adsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
qcom,no-wake-svc = <0x190>;
|
|
};
|
|
|
|
qcom,apr_tal_rpmsg {
|
|
qcom,glink-channels = "apr_audio_svc";
|
|
qcom,intents = <0x200 20>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 64>;
|
|
};
|
|
|
|
qcom,adsp_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
};
|
|
};
|
|
};
|
|
|
|
cdsp_pas: remoteproc-cdsp@8300000 {
|
|
compatible = "qcom,kona-cdsp-pas";
|
|
reg = <0x8300000 0x100000>;
|
|
status = "ok";
|
|
|
|
cx-supply = <&VDD_CX_LEVEL>;
|
|
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
|
reg-names = "cx";
|
|
|
|
memory-region = <&rproc_cdsp_mem>;
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
qcom,signal-aop;
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
interconnects = <&compute_noc MASTER_NPU &compute_noc SLAVE_CDSP_MEM_NOC>;
|
|
interconnect-names = "rproc_ddr";
|
|
|
|
/* Inputs from turing */
|
|
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
|
|
<&cdsp_smp2p_in 0 0>,
|
|
<&cdsp_smp2p_in 2 0>,
|
|
<&cdsp_smp2p_in 1 0>,
|
|
<&cdsp_smp2p_in 3 0>,
|
|
<&cdsp_smp2p_in 7 0>;
|
|
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"handover",
|
|
"ready",
|
|
"stop-ack",
|
|
"shutdown-ack";
|
|
|
|
/* Outputs to turing */
|
|
qcom,smem-states = <&cdsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <5>;
|
|
transport = "smem";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "cdsp_smem";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "cdsp";
|
|
qcom,glink-label = "cdsp";
|
|
|
|
qcom,cdsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 64>;
|
|
};
|
|
|
|
qcom,msm_cdsprm_rpmsg {
|
|
compatible = "qcom,msm-cdsprm-rpmsg";
|
|
qcom,glink-channels = "cdsprmglink-apps-dsp";
|
|
qcom,intents = <0x20 12>;
|
|
|
|
msm_cdsp_rm: qcom,msm_cdsp_rm {
|
|
compatible = "qcom,msm-cdsp-rm";
|
|
qcom,qos-latency-us = <44>;
|
|
qcom,qos-maxhold-ms = <20>;
|
|
qcom,compute-cx-limit-en;
|
|
qcom,compute-priority-mode = <2>;
|
|
#cooling-cells = <2>;
|
|
};
|
|
|
|
msm_hvx_rm: qcom,msm_hvx_rm {
|
|
compatible = "qcom,msm-hvx-rm";
|
|
#cooling-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,cdsp_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
};
|
|
};
|
|
};
|
|
|
|
slpi_pas: remoteproc-slpi@5c00000 {
|
|
compatible = "qcom,kona-slpi-pas";
|
|
reg = <0x5c00000 0x4000>;
|
|
status = "ok";
|
|
|
|
cx-supply = <&L11A_LEVEL>;
|
|
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
mx-supply = <&L4A_LEVEL>;
|
|
mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
reg-names = "cx", "mx";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
|
|
memory-region = <&rproc_slpi_mem>;
|
|
|
|
qcom,signal-aop;
|
|
|
|
/* Inputs from ssc */
|
|
interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
|
|
<&dsps_smp2p_in 0 0>,
|
|
<&dsps_smp2p_in 2 0>,
|
|
<&dsps_smp2p_in 1 0>,
|
|
<&dsps_smp2p_in 3 0>,
|
|
<&dsps_smp2p_in 7 0>;
|
|
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"handover",
|
|
"ready",
|
|
"stop-ack",
|
|
"shutdown-ack";
|
|
|
|
/* Outputs to turing */
|
|
qcom,smem-states = <&dsps_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <3>;
|
|
transport = "smem";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "dsps_smem";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_SLPI
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "slpi";
|
|
qcom,glink-label = "dsps";
|
|
|
|
qcom,slpi_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,net-id = <2>;
|
|
qcom,low-latency;
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 64>;
|
|
};
|
|
|
|
qcom,slpi_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
};
|
|
};
|
|
};
|
|
|
|
spss_pas: remoteproc-spss@1880000 {
|
|
compatible = "qcom,kona-spss-pas";
|
|
ranges;
|
|
reg = <0x188101c 0x4>,
|
|
<0x1881024 0x4>,
|
|
<0x1881028 0x4>,
|
|
<0x188103c 0x4>,
|
|
<0x1881100 0x4>,
|
|
<0x1882014 0x4>;
|
|
reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask",
|
|
"rmb_err", "rmb_general_purpose", "rmb_err_spare2";
|
|
interrupts = <0 352 1>;
|
|
|
|
cx-supply = <&VDD_CX_LEVEL>;
|
|
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
|
mx-supply = <&VDD_MX_LEVEL>;
|
|
mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
qcom,proxy-clock-names = "xo";
|
|
status = "ok";
|
|
|
|
memory-region = <&rproc_spss_mem>;
|
|
qcom,spss-scsr-bits = <24 25>;
|
|
qcom,extra-size = <4096>;
|
|
qcom,signal-aop;
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <8>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "spss_spss";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_SPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
reg = <0x1885008 0x8>,
|
|
<0x1885010 0x4>;
|
|
reg-names = "qcom,spss-addr",
|
|
"qcom,spss-size";
|
|
|
|
label = "spss";
|
|
qcom,glink-label = "spss";
|
|
};
|
|
};
|
|
|
|
qcom,smp2p_sleepstate {
|
|
compatible = "qcom,smp2p-sleepstate";
|
|
qcom,smem-states = <&sleepstate_smp2p_out 0>;
|
|
interrupt-parent = <&sleepstate_smp2p_in>;
|
|
interrupts = <0 0>;
|
|
interrupt-names = "smp2p-sleepstate-in";
|
|
};
|
|
|
|
qcom,msm-cdsp-loader {
|
|
compatible = "qcom,cdsp-loader";
|
|
qcom,proc-img-to-load = "cdsp";
|
|
qcom,rproc-handle = <&cdsp_pas>;
|
|
};
|
|
|
|
qcom,msm-adsprpc-mem {
|
|
compatible = "qcom,msm-adsprpc-mem-region";
|
|
memory-region = <&adsp_mem>;
|
|
restrict-access;
|
|
};
|
|
|
|
msm_fastrpc: qcom,msm_fastrpc {
|
|
compatible = "qcom,msm-fastrpc-compute";
|
|
qcom,adsp-remoteheap-vmid = <22 37>;
|
|
qcom,fastrpc-adsp-audio-pdr;
|
|
qcom,fastrpc-slpi-sensors-pdr;
|
|
qcom,rpc-latency-us = <235>;
|
|
qcom,qos-cores = <0 1 2 3>;
|
|
|
|
qcom,msm_fastrpc_compute_cb1 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1001 0x0460>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb2 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1002 0x0460>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb3 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1003 0x0460>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb4 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1004 0x0460>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb5 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1005 0x0460>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb6 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1006 0x0460>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb7 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1007 0x0460>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb8 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1008 0x0460>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb9 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
qcom,secure-context-bank;
|
|
iommus = <&apps_smmu 0x1009 0x0460>;
|
|
qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb10 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x1803 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb11 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x1804 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb12 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x1805 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb13 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "sdsprpc-smd";
|
|
iommus = <&apps_smmu 0x0541 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb14 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "sdsprpc-smd";
|
|
iommus = <&apps_smmu 0x0542 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb15 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "sdsprpc-smd";
|
|
iommus = <&apps_smmu 0x0543 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable", "HUPCF";
|
|
shared-cb = <4>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
|
|
qcom,spcom {
|
|
compatible = "qcom,spcom";
|
|
|
|
qcom,rproc-handle = <&spss_pas>;
|
|
qcom,boot-enabled;
|
|
/* predefined channels, remote side is server */
|
|
qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
|
|
/* sp2soc rmb shared register physical address and bmsk */
|
|
qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
|
|
qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
|
|
qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;
|
|
/* soc2sp rmb shared register physical address */
|
|
qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
|
|
qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
|
|
status = "ok";
|
|
};
|
|
|
|
spss_utils: qcom,spss_utils {
|
|
compatible = "qcom,spss-utils";
|
|
/* spss fuses physical address */
|
|
qcom,rproc-handle = <&spss_pas>;
|
|
qcom,spss-fuse1-addr = <0x00780234>;
|
|
qcom,spss-fuse1-bit = <27>;
|
|
qcom,spss-fuse2-addr = <0x00780234>;
|
|
qcom,spss-fuse2-bit = <26>;
|
|
qcom,spss-dev-firmware-name = "spss1d.mdt"; /* 8 chars max */
|
|
qcom,spss-test-firmware-name = "spss1t.mdt"; /* 8 chars max */
|
|
qcom,spss-prod-firmware-name = "spss1p.mdt"; /* 8 chars max */
|
|
qcom,spss-debug-reg-addr = <0x01886020>;
|
|
qcom,spss-debug-reg-addr1 = <0x01888020>;
|
|
qcom,spss-debug-reg-addr3 = <0x0188C020>;
|
|
qcom,spss-emul-type-reg-addr = <0x01fc8004>;
|
|
pil-mem = <&rproc_spss_mem>;
|
|
qcom,pil-addr = <0x8BE00000>; // backward compatible
|
|
qcom,pil-size = <0x0F0000>; // padding to 960KB
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-apr-apps2 {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "apr_apps2";
|
|
qcom,glinkpkt-dev-name = "apr_apps2";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
|
|
qcom,glinkpkt-slate-ssc-hal {
|
|
qcom,glinkpkt-edge = "slate";
|
|
qcom,glinkpkt-ch-name = "ssc_hal";
|
|
qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_hal";
|
|
qcom,glinkpkt-enable-ch-close;
|
|
};
|
|
};
|
|
|
|
qcom,glink {
|
|
compatible = "qcom,glink";
|
|
};
|
|
|
|
dcc: dcc_v2@1023000 {
|
|
compatible = "qcom,dcc-v2";
|
|
reg = <0x1023000 0x1000>,
|
|
<0x103a000 0x6000>;
|
|
reg-names = "dcc-base", "dcc-ram-base";
|
|
|
|
dcc-ram-offset = <0x1a000>;
|
|
|
|
link_list1 {
|
|
qcom,curr-link-list = <3>;
|
|
qcom,data-sink = "sram";
|
|
qcom,link-list = <DCC_READ 0x18220d14 3 0>,
|
|
<DCC_READ 0x18220d30 4 0>,
|
|
<DCC_READ 0x18220d44 4 0>,
|
|
<DCC_READ 0x18220d58 4 0>,
|
|
<DCC_READ 0x18220fb4 3 0>,
|
|
<DCC_READ 0x18220fd0 4 0>,
|
|
<DCC_READ 0x18220fe4 4 0>,
|
|
<DCC_READ 0x18220ff8 4 0>,
|
|
<DCC_READ 0x18220d04 1 0>,
|
|
<DCC_READ 0x18220d00 1 0>,
|
|
<DCC_READ 0x18000024 1 0>,
|
|
<DCC_READ 0x18000040 4 0>,
|
|
<DCC_READ 0x18010024 1 0>,
|
|
<DCC_READ 0x18010040 4 0>,
|
|
<DCC_READ 0x18020024 1 0>,
|
|
<DCC_READ 0x18020040 4 0>,
|
|
<DCC_READ 0x18030024 1 0>,
|
|
<DCC_READ 0x18030040 4 0>,
|
|
<DCC_READ 0x18040024 1 0>,
|
|
<DCC_READ 0x18040040 4 0>,
|
|
<DCC_READ 0x18050024 1 0>,
|
|
<DCC_READ 0x18050040 4 0>,
|
|
<DCC_READ 0x18060024 1 0>,
|
|
<DCC_READ 0x18060040 4 0>,
|
|
<DCC_READ 0x18070024 1 0>,
|
|
<DCC_READ 0x18070040 4 0>,
|
|
<DCC_READ 0x18080104 1 0>,
|
|
<DCC_READ 0x18080168 1 0>,
|
|
<DCC_READ 0x18080198 1 0>,
|
|
<DCC_READ 0x18080128 1 0>,
|
|
<DCC_READ 0x18080024 1 0>,
|
|
<DCC_READ 0x18080040 3 0>,
|
|
<DCC_READ 0x18200400 3 0>,
|
|
<DCC_READ 0x0b201020 2 0>,
|
|
<DCC_READ 0x0b204520 1 0>,
|
|
<DCC_READ 0x1800005c 1 0>,
|
|
<DCC_READ 0x1801005c 1 0>,
|
|
<DCC_READ 0x1802005c 1 0>,
|
|
<DCC_READ 0x1803005c 1 0>,
|
|
<DCC_READ 0x1804005c 1 0>,
|
|
<DCC_READ 0x1805005c 1 0>,
|
|
<DCC_READ 0x1806005c 1 0>,
|
|
<DCC_READ 0x1807005c 1 0>,
|
|
<DCC_READ 0x18101908 1 0>,
|
|
<DCC_READ 0x18101c18 1 0>,
|
|
<DCC_READ 0x18390810 1 0>,
|
|
<DCC_READ 0x18390c50 1 0>,
|
|
<DCC_READ 0x18390814 1 0>,
|
|
<DCC_READ 0x18390c54 1 0>,
|
|
<DCC_READ 0x18390818 1 0>,
|
|
<DCC_READ 0x18390c58 1 0>,
|
|
<DCC_READ 0x18393a84 2 0>,
|
|
<DCC_READ 0x18100908 1 0>,
|
|
<DCC_READ 0x18100c18 1 0>,
|
|
<DCC_READ 0x183a0810 1 0>,
|
|
<DCC_READ 0x183a0c50 1 0>,
|
|
<DCC_READ 0x183a0814 1 0>,
|
|
<DCC_READ 0x183a0c54 1 0>,
|
|
<DCC_READ 0x183a0818 1 0>,
|
|
<DCC_READ 0x183a0c58 1 0>,
|
|
<DCC_READ 0x183a3a84 2 0>,
|
|
<DCC_READ 0x18393500 1 0>,
|
|
<DCC_READ 0x18393580 1 0>,
|
|
<DCC_READ 0x183a3500 1 0>,
|
|
<DCC_READ 0x183a3580 1 0>,
|
|
<DCC_READ 0x18282000 4 0>,
|
|
<DCC_READ 0x18282028 1 0>,
|
|
<DCC_READ 0x18282038 1 0>,
|
|
<DCC_READ 0x18282080 5 0>,
|
|
<DCC_READ 0x18286000 4 0>,
|
|
<DCC_READ 0x18286028 1 0>,
|
|
<DCC_READ 0x18286038 1 0>,
|
|
<DCC_READ 0x18286080 5 0>,
|
|
<DCC_READ 0x0c201244 1 0>,
|
|
<DCC_READ 0x0c202244 1 0>,
|
|
<DCC_READ 0x18300000 1 0>,
|
|
<DCC_READ 0x1829208c 1 0>,
|
|
<DCC_READ 0x18292098 1 0>,
|
|
<DCC_READ 0x18292098 1 0>,
|
|
<DCC_READ 0x1829608c 1 0>,
|
|
<DCC_READ 0x18296098 1 0>,
|
|
<DCC_READ 0x18296098 1 0>,
|
|
<DCC_READ 0x091a9020 1 0>,
|
|
<DCC_READ_WRITE 0x5 0x1 0>,
|
|
<DCC_READ 0x09102008 1 0>,
|
|
<DCC_READ_WRITE 0x2 0x2 0>,
|
|
<DCC_READ 0x09142008 1 0>,
|
|
<DCC_READ_WRITE 0x2 0x2 0>,
|
|
<DCC_READ 0x09102408 1 0>,
|
|
<DCC_READ_WRITE 0x2 0x2 0>,
|
|
<DCC_READ 0x09142408 1 0>,
|
|
<DCC_READ_WRITE 0x2 0x2 0>,
|
|
<DCC_READ 0x09103808 1 0>,
|
|
<DCC_LOOP 3 0 0>,
|
|
<DCC_READ 0x09103810 1 0>,
|
|
<DCC_READ 0x09103814 1 0>,
|
|
<DCC_LOOP 1 0 0>,
|
|
<DCC_READ 0x09103888 1 0>,
|
|
<DCC_LOOP 2 0 0>,
|
|
<DCC_READ 0x09103890 1 0>,
|
|
<DCC_READ 0x09103894 1 0>,
|
|
<DCC_LOOP 1 0 0>,
|
|
<DCC_READ 0x09143808 1 0>,
|
|
<DCC_LOOP 3 0 0>,
|
|
<DCC_READ 0x09143810 1 0>,
|
|
<DCC_READ 0x09143814 1 0>,
|
|
<DCC_LOOP 1 0 0>,
|
|
<DCC_READ 0x09143888 1 0>,
|
|
<DCC_LOOP 2 0 0>,
|
|
<DCC_READ 0x09143890 1 0>,
|
|
<DCC_READ 0x09143894 1 0>,
|
|
<DCC_LOOP 1 0 0>,
|
|
<DCC_READ 0x09182808 1 0>,
|
|
<DCC_LOOP 2 0 0>,
|
|
<DCC_READ 0x09182810 1 0>,
|
|
<DCC_READ 0x09182814 1 0>,
|
|
<DCC_LOOP 1 0 0>,
|
|
<DCC_READ 0x09182888 1 0>,
|
|
<DCC_LOOP 3 0 0>,
|
|
<DCC_READ 0x09182890 1 0>,
|
|
<DCC_READ 0x09182894 1 0>,
|
|
<DCC_LOOP 1 0 0>,
|
|
<DCC_READ 0x09103008 1 0>,
|
|
<DCC_READ 0x0910300c 1 0>,
|
|
<DCC_WRITE 0x09103028 0x00000001 1>,
|
|
<DCC_LOOP 41 0 0>,
|
|
<DCC_READ 0x09103010 1 0>,
|
|
<DCC_READ 0x09103014 1 0>,
|
|
<DCC_LOOP 1 0 0>,
|
|
<DCC_READ 0x09103408 1 0>,
|
|
<DCC_READ 0x0910340c 1 0>,
|
|
<DCC_WRITE 0x09103428 0x00000001 1>,
|
|
<DCC_LOOP 41 0 0>,
|
|
<DCC_READ 0x09103410 1 0>,
|
|
<DCC_READ 0x09103414 1 0>,
|
|
<DCC_LOOP 1 0 0>,
|
|
<DCC_READ 0x09143008 1 0>,
|
|
<DCC_READ 0x0914300c 1 0>,
|
|
<DCC_WRITE 0x09143028 0x00000001 1>,
|
|
<DCC_LOOP 41 0 0>,
|
|
<DCC_READ 0x09143010 1 0>,
|
|
<DCC_READ 0x09143014 1 0>,
|
|
<DCC_LOOP 1 0 0>,
|
|
<DCC_READ 0x09143408 1 0>,
|
|
<DCC_READ 0x0914340c 1 0>,
|
|
<DCC_WRITE 0x09143428 0x00000001 1>,
|
|
<DCC_LOOP 41 0 0>,
|
|
<DCC_READ 0x09143410 1 0>,
|
|
<DCC_READ 0x09143414 1 0>,
|
|
<DCC_LOOP 1 0 0>,
|
|
<DCC_READ 0x09182008 1 0>,
|
|
<DCC_READ 0x0918200c 1 0>,
|
|
<DCC_WRITE 0x09182028 0x00000001 1>,
|
|
<DCC_LOOP 11 0 0>,
|
|
<DCC_READ 0x09182010 1 0>,
|
|
<DCC_READ 0x09182014 1 0>,
|
|
<DCC_LOOP 1 0 0>,
|
|
<DCC_READ 0x09182408 1 0>,
|
|
<DCC_READ 0x0918240c 1 0>,
|
|
<DCC_WRITE 0x09182428 0x00000001 1>,
|
|
<DCC_LOOP 11 0 0>,
|
|
<DCC_READ 0x09182410 1 0>,
|
|
<DCC_READ 0x09182414 1 0>,
|
|
<DCC_LOOP 1 0 0>;
|
|
};
|
|
|
|
link_list2 {
|
|
qcom,curr-link-list = <6>;
|
|
qcom,data-sink = "sram";
|
|
qcom,link-list = <DCC_READ 0x9050078 1 0>,
|
|
<DCC_READ 0x9050110 8 0>,
|
|
<DCC_READ 0x9080058 2 0>,
|
|
<DCC_READ 0x90800c8 1 0>,
|
|
<DCC_READ 0x90800d4 1 0>,
|
|
<DCC_READ 0x90800e0 1 0>,
|
|
<DCC_READ 0x90800ec 1 0>,
|
|
<DCC_READ 0x90800f8 1 0>,
|
|
<DCC_READ 0x908401c 1 0>,
|
|
<DCC_READ 0x908403c 1 0>,
|
|
<DCC_READ 0x908404c 2 0>,
|
|
<DCC_READ 0x90840d4 1 0>,
|
|
<DCC_READ 0x9084204 1 0>,
|
|
<DCC_READ 0x908420c 1 0>,
|
|
<DCC_READ 0x9084250 2 0>,
|
|
<DCC_READ 0x9084260 3 0>,
|
|
<DCC_READ 0x9084280 1 0>,
|
|
<DCC_READ 0x90ba280 1 0>,
|
|
<DCC_READ 0x90ba288 7 0>,
|
|
<DCC_READ 0x9258610 4 0>,
|
|
<DCC_READ 0x92d8610 4 0>,
|
|
<DCC_READ 0x9358610 4 0>,
|
|
<DCC_READ 0x93d8610 4 0>,
|
|
<DCC_READ 0x9220344 8 0>,
|
|
<DCC_READ 0x9220370 6 0>,
|
|
<DCC_READ 0x9220480 1 0>,
|
|
<DCC_READ 0x9222400 1 0>,
|
|
<DCC_READ 0x922240c 1 0>,
|
|
<DCC_READ 0x9223214 2 0>,
|
|
<DCC_READ 0x9223220 3 0>,
|
|
<DCC_READ 0x9223308 1 0>,
|
|
<DCC_READ 0x9223318 1 0>,
|
|
<DCC_READ 0x9232100 1 0>,
|
|
<DCC_READ 0x9236040 6 0>,
|
|
<DCC_READ 0x92360b0 1 0>,
|
|
<DCC_READ 0x923e030 2 0>,
|
|
<DCC_READ 0x9241000 1 0>,
|
|
<DCC_READ 0x9242028 1 0>,
|
|
<DCC_READ 0x9242044 3 0>,
|
|
<DCC_READ 0x9242070 1 0>,
|
|
<DCC_READ 0x9248030 1 0>,
|
|
<DCC_READ 0x9248048 8 0>,
|
|
<DCC_READ 0x92a0344 8 0>,
|
|
<DCC_READ 0x92a0370 6 0>,
|
|
<DCC_READ 0x92a0480 1 0>,
|
|
<DCC_READ 0x92a2400 1 0>,
|
|
<DCC_READ 0x92a240c 1 0>,
|
|
<DCC_READ 0x92a3214 2 0>,
|
|
<DCC_READ 0x92a3220 3 0>,
|
|
<DCC_READ 0x92a3308 1 0>,
|
|
<DCC_READ 0x92a3318 1 0>,
|
|
<DCC_READ 0x92b2100 1 0>,
|
|
<DCC_READ 0x92b6040 6 0>,
|
|
<DCC_READ 0x92b60b0 1 0>,
|
|
<DCC_READ 0x92be030 2 0>,
|
|
<DCC_READ 0x92c1000 1 0>,
|
|
<DCC_READ 0x92c2028 1 0>,
|
|
<DCC_READ 0x92c2044 3 0>,
|
|
<DCC_READ 0x92c2070 1 0>,
|
|
<DCC_READ 0x92c8030 1 0>,
|
|
<DCC_READ 0x92c8048 8 0>,
|
|
<DCC_READ 0x9320344 8 0>,
|
|
<DCC_READ 0x9320370 6 0>,
|
|
<DCC_READ 0x9320480 1 0>,
|
|
<DCC_READ 0x9322400 1 0>,
|
|
<DCC_READ 0x932240c 1 0>,
|
|
<DCC_READ 0x9323214 2 0>,
|
|
<DCC_READ 0x9323220 3 0>,
|
|
<DCC_READ 0x9323308 1 0>,
|
|
<DCC_READ 0x9323318 1 0>,
|
|
<DCC_READ 0x9332100 1 0>,
|
|
<DCC_READ 0x9336040 6 0>,
|
|
<DCC_READ 0x93360b0 1 0>,
|
|
<DCC_READ 0x933e030 2 0>,
|
|
<DCC_READ 0x9341000 1 0>,
|
|
<DCC_READ 0x9342028 1 0>,
|
|
<DCC_READ 0x9342044 3 0>,
|
|
<DCC_READ 0x9342070 1 0>,
|
|
<DCC_READ 0x9348030 1 0>,
|
|
<DCC_READ 0x9348048 8 0>,
|
|
<DCC_READ 0x93a0344 8 0>,
|
|
<DCC_READ 0x93a0370 6 0>,
|
|
<DCC_READ 0x93a0480 1 0>,
|
|
<DCC_READ 0x93a2400 1 0>,
|
|
<DCC_READ 0x93a240c 1 0>,
|
|
<DCC_READ 0x93a3214 2 0>,
|
|
<DCC_READ 0x93a3220 3 0>,
|
|
<DCC_READ 0x93a3308 1 0>,
|
|
<DCC_READ 0x93a3318 1 0>,
|
|
<DCC_READ 0x93b2100 1 0>,
|
|
<DCC_READ 0x93b6040 6 0>,
|
|
<DCC_READ 0x93b60b0 1 0>,
|
|
<DCC_READ 0x93be030 2 0>,
|
|
<DCC_READ 0x93c1000 1 0>,
|
|
<DCC_READ 0x93c2028 1 0>,
|
|
<DCC_READ 0x93c2044 3 0>,
|
|
<DCC_READ 0x93c2070 1 0>,
|
|
<DCC_READ 0x93c8030 1 0>,
|
|
<DCC_READ 0x93c8048 8 0>,
|
|
<DCC_READ 0x9270080 1 0>,
|
|
<DCC_READ 0x9270400 1 0>,
|
|
<DCC_READ 0x9270410 6 0>,
|
|
<DCC_READ 0x9270430 1 0>,
|
|
<DCC_READ 0x9270440 1 0>,
|
|
<DCC_READ 0x9270448 1 0>,
|
|
<DCC_READ 0x92704a0 1 0>,
|
|
<DCC_READ 0x92704b0 1 0>,
|
|
<DCC_READ 0x92704b8 2 0>,
|
|
<DCC_READ 0x92704d0 1 0>,
|
|
<DCC_READ 0x9271400 1 0>,
|
|
<DCC_READ 0x92753b0 1 0>,
|
|
<DCC_READ 0x9275c1c 1 0>,
|
|
<DCC_READ 0x9275c2c 1 0>,
|
|
<DCC_READ 0x9275c38 1 0>,
|
|
<DCC_READ 0x9276418 2 0>,
|
|
<DCC_READ 0x92f0080 1 0>,
|
|
<DCC_READ 0x92f0400 1 0>,
|
|
<DCC_READ 0x92f0410 6 0>,
|
|
<DCC_READ 0x92f0430 1 0>,
|
|
<DCC_READ 0x92f0440 1 0>,
|
|
<DCC_READ 0x92f0448 1 0>,
|
|
<DCC_READ 0x92f04a0 1 0>,
|
|
<DCC_READ 0x92f04b0 1 0>,
|
|
<DCC_READ 0x92f04b8 2 0>,
|
|
<DCC_READ 0x92f04d0 1 0>,
|
|
<DCC_READ 0x92f1400 1 0>,
|
|
<DCC_READ 0x92f53b0 1 0>,
|
|
<DCC_READ 0x92f5c1c 1 0>,
|
|
<DCC_READ 0x92f5c2c 1 0>,
|
|
<DCC_READ 0x92f5c38 1 0>,
|
|
<DCC_READ 0x92f6418 2 0>,
|
|
<DCC_READ 0x9370080 1 0>,
|
|
<DCC_READ 0x9370400 1 0>,
|
|
<DCC_READ 0x9370410 6 0>,
|
|
<DCC_READ 0x9370430 1 0>,
|
|
<DCC_READ 0x9370440 1 0>,
|
|
<DCC_READ 0x9370448 1 0>,
|
|
<DCC_READ 0x93704a0 1 0>,
|
|
<DCC_READ 0x93704b0 1 0>,
|
|
<DCC_READ 0x93704b8 2 0>,
|
|
<DCC_READ 0x93704d0 1 0>,
|
|
<DCC_READ 0x9371400 1 0>,
|
|
<DCC_READ 0x93753b0 1 0>,
|
|
<DCC_READ 0x9375c1c 1 0>,
|
|
<DCC_READ 0x9375c2c 1 0>,
|
|
<DCC_READ 0x9375c38 1 0>,
|
|
<DCC_READ 0x9376418 2 0>,
|
|
<DCC_READ 0x93f0080 1 0>,
|
|
<DCC_READ 0x93f0400 1 0>,
|
|
<DCC_READ 0x93f0410 6 0>,
|
|
<DCC_READ 0x93f0430 1 0>,
|
|
<DCC_READ 0x93f0440 1 0>,
|
|
<DCC_READ 0x93f0448 1 0>,
|
|
<DCC_READ 0x93f04a0 1 0>,
|
|
<DCC_READ 0x93f04b0 1 0>,
|
|
<DCC_READ 0x93f04b8 2 0>,
|
|
<DCC_READ 0x93f04d0 1 0>,
|
|
<DCC_READ 0x93f1400 1 0>,
|
|
<DCC_READ 0x93f53b0 1 0>,
|
|
<DCC_READ 0x93f5c1c 1 0>,
|
|
<DCC_READ 0x93f5c2c 1 0>,
|
|
<DCC_READ 0x93f5c38 1 0>,
|
|
<DCC_READ 0x93f6418 2 0>,
|
|
<DCC_READ 0x9260080 1 0>,
|
|
<DCC_READ 0x9260400 1 0>,
|
|
<DCC_READ 0x9260410 3 0>,
|
|
<DCC_READ 0x9260420 2 0>,
|
|
<DCC_READ 0x9260430 1 0>,
|
|
<DCC_READ 0x9260440 1 0>,
|
|
<DCC_READ 0x9260448 1 0>,
|
|
<DCC_READ 0x92604a0 1 0>,
|
|
<DCC_READ 0x92604b0 1 0>,
|
|
<DCC_READ 0x92604b8 2 0>,
|
|
<DCC_READ 0x92604d0 2 0>,
|
|
<DCC_READ 0x9261400 1 0>,
|
|
<DCC_READ 0x9263410 1 0>,
|
|
<DCC_READ 0x92653b0 1 0>,
|
|
<DCC_READ 0x9265804 1 0>,
|
|
<DCC_READ 0x9265b1c 1 0>,
|
|
<DCC_READ 0x9265b2c 1 0>,
|
|
<DCC_READ 0x9265b38 1 0>,
|
|
<DCC_READ 0x9269100 1 0>,
|
|
<DCC_READ 0x9269110 1 0>,
|
|
<DCC_READ 0x9269120 1 0>,
|
|
<DCC_READ 0x92e0080 1 0>,
|
|
<DCC_READ 0x92e0400 1 0>,
|
|
<DCC_READ 0x92e0410 3 0>,
|
|
<DCC_READ 0x92e0420 2 0>,
|
|
<DCC_READ 0x92e0430 1 0>,
|
|
<DCC_READ 0x92e0440 1 0>,
|
|
<DCC_READ 0x92e0448 1 0>,
|
|
<DCC_READ 0x92e04a0 1 0>,
|
|
<DCC_READ 0x92e04b0 1 0>,
|
|
<DCC_READ 0x92e04b8 2 0>,
|
|
<DCC_READ 0x92e04d0 2 0>,
|
|
<DCC_READ 0x92e1400 1 0>,
|
|
<DCC_READ 0x92e3410 1 0>,
|
|
<DCC_READ 0x92e53b0 1 0>,
|
|
<DCC_READ 0x92e5804 1 0>,
|
|
<DCC_READ 0x92e5b1c 1 0>,
|
|
<DCC_READ 0x92e5b2c 1 0>,
|
|
<DCC_READ 0x92e5b38 1 0>,
|
|
<DCC_READ 0x92e9100 1 0>,
|
|
<DCC_READ 0x92e9110 1 0>,
|
|
<DCC_READ 0x92e9120 1 0>,
|
|
<DCC_READ 0x9360080 1 0>,
|
|
<DCC_READ 0x9360400 1 0>,
|
|
<DCC_READ 0x9360410 3 0>,
|
|
<DCC_READ 0x9360420 2 0>,
|
|
<DCC_READ 0x9360430 1 0>,
|
|
<DCC_READ 0x9360440 1 0>,
|
|
<DCC_READ 0x9360448 1 0>,
|
|
<DCC_READ 0x93604a0 1 0>,
|
|
<DCC_READ 0x93604b0 1 0>,
|
|
<DCC_READ 0x93604b8 2 0>,
|
|
<DCC_READ 0x93604d0 2 0>,
|
|
<DCC_READ 0x9361400 1 0>,
|
|
<DCC_READ 0x9363410 1 0>,
|
|
<DCC_READ 0x93653b0 1 0>,
|
|
<DCC_READ 0x9365804 1 0>,
|
|
<DCC_READ 0x9365b1c 1 0>,
|
|
<DCC_READ 0x9365b2c 1 0>,
|
|
<DCC_READ 0x9365b38 1 0>,
|
|
<DCC_READ 0x9369100 1 0>,
|
|
<DCC_READ 0x9369110 1 0>,
|
|
<DCC_READ 0x9369120 1 0>,
|
|
<DCC_READ 0x93e0080 1 0>,
|
|
<DCC_READ 0x93e0400 1 0>,
|
|
<DCC_READ 0x93e0410 3 0>,
|
|
<DCC_READ 0x93e0420 2 0>,
|
|
<DCC_READ 0x93e0430 1 0>,
|
|
<DCC_READ 0x93e0440 1 0>,
|
|
<DCC_READ 0x93e0448 1 0>,
|
|
<DCC_READ 0x93e04a0 1 0>,
|
|
<DCC_READ 0x93e04b0 1 0>,
|
|
<DCC_READ 0x93e04b8 2 0>,
|
|
<DCC_READ 0x93e04d0 2 0>,
|
|
<DCC_READ 0x93e1400 1 0>,
|
|
<DCC_READ 0x93e3410 1 0>,
|
|
<DCC_READ 0x93e53b0 1 0>,
|
|
<DCC_READ 0x93e5804 1 0>,
|
|
<DCC_READ 0x93e5b1c 1 0>,
|
|
<DCC_READ 0x93e5b2c 1 0>,
|
|
<DCC_READ 0x93e5b38 1 0>,
|
|
<DCC_READ 0x93e9100 1 0>,
|
|
<DCC_READ 0x93e9110 1 0>,
|
|
<DCC_READ 0x93e9120 1 0>,
|
|
<DCC_READ 0x96b0868 1 0>,
|
|
<DCC_READ 0x96b0870 1 0>,
|
|
<DCC_READ 0x96b1004 1 0>,
|
|
<DCC_READ 0x96b100c 1 0>,
|
|
<DCC_READ 0x96b1014 1 0>,
|
|
<DCC_READ 0x96b1204 1 0>,
|
|
<DCC_READ 0x96b120c 1 0>,
|
|
<DCC_READ 0x96b1214 1 0>,
|
|
<DCC_READ 0x96b1504 1 0>,
|
|
<DCC_READ 0x96b150c 1 0>,
|
|
<DCC_READ 0x96b1514 1 0>,
|
|
<DCC_READ 0x96b1604 1 0>,
|
|
<DCC_READ 0x96b8100 1 0>,
|
|
<DCC_READ 0x96b813c 1 0>,
|
|
<DCC_READ 0x96b8500 1 0>,
|
|
<DCC_READ 0x96b853c 1 0>,
|
|
<DCC_READ 0x96b8a04 1 0>,
|
|
<DCC_READ 0x96b8a18 1 0>,
|
|
<DCC_READ 0x96b8ea8 1 0>,
|
|
<DCC_READ 0x96b9044 1 0>,
|
|
<DCC_READ 0x96b904c 1 0>,
|
|
<DCC_READ 0x96b9054 1 0>,
|
|
<DCC_READ 0x96b905c 1 0>,
|
|
<DCC_READ 0x96b910c 2 0>,
|
|
<DCC_READ 0x96b9204 1 0>,
|
|
<DCC_READ 0x96b920c 1 0>,
|
|
<DCC_READ 0x96b9238 1 0>,
|
|
<DCC_READ 0x96b9240 1 0>,
|
|
<DCC_READ 0x96b926c 1 0>,
|
|
<DCC_READ 0x96b9394 1 0>,
|
|
<DCC_READ 0x96b939c 1 0>,
|
|
<DCC_READ 0x96b9704 1 0>,
|
|
<DCC_READ 0x96b970c 1 0>,
|
|
<DCC_READ 0x96f0868 1 0>,
|
|
<DCC_READ 0x96f0870 1 0>,
|
|
<DCC_READ 0x96f1004 1 0>,
|
|
<DCC_READ 0x96f100c 1 0>,
|
|
<DCC_READ 0x96f1014 1 0>,
|
|
<DCC_READ 0x96f1204 1 0>,
|
|
<DCC_READ 0x96f120c 1 0>,
|
|
<DCC_READ 0x96f1214 1 0>,
|
|
<DCC_READ 0x96f1504 1 0>,
|
|
<DCC_READ 0x96f150c 1 0>,
|
|
<DCC_READ 0x96f1514 1 0>,
|
|
<DCC_READ 0x96f1604 1 0>,
|
|
<DCC_READ 0x96f8100 1 0>,
|
|
<DCC_READ 0x96f813c 1 0>,
|
|
<DCC_READ 0x96f8500 1 0>,
|
|
<DCC_READ 0x96f853c 1 0>,
|
|
<DCC_READ 0x96f8a04 1 0>,
|
|
<DCC_READ 0x96f8a18 1 0>,
|
|
<DCC_READ 0x96f8ea8 1 0>,
|
|
<DCC_READ 0x96f9044 1 0>,
|
|
<DCC_READ 0x96f904c 1 0>,
|
|
<DCC_READ 0x96f9054 1 0>,
|
|
<DCC_READ 0x96f905c 1 0>,
|
|
<DCC_READ 0x96f910c 2 0>,
|
|
<DCC_READ 0x96f9204 1 0>,
|
|
<DCC_READ 0x96f920c 1 0>,
|
|
<DCC_READ 0x96f9238 1 0>,
|
|
<DCC_READ 0x96f9240 1 0>,
|
|
<DCC_READ 0x96f926c 1 0>,
|
|
<DCC_READ 0x96f9394 1 0>,
|
|
<DCC_READ 0x96f939c 1 0>,
|
|
<DCC_READ 0x96f9704 1 0>,
|
|
<DCC_READ 0x96f970c 1 0>,
|
|
<DCC_READ 0x9730868 1 0>,
|
|
<DCC_READ 0x9730870 1 0>,
|
|
<DCC_READ 0x9731004 1 0>,
|
|
<DCC_READ 0x973100c 1 0>,
|
|
<DCC_READ 0x9731014 1 0>,
|
|
<DCC_READ 0x9731204 1 0>,
|
|
<DCC_READ 0x973120c 1 0>,
|
|
<DCC_READ 0x9731214 1 0>,
|
|
<DCC_READ 0x9731504 1 0>,
|
|
<DCC_READ 0x973150c 1 0>,
|
|
<DCC_READ 0x9731514 1 0>,
|
|
<DCC_READ 0x9731604 1 0>,
|
|
<DCC_READ 0x9738100 1 0>,
|
|
<DCC_READ 0x973813c 1 0>,
|
|
<DCC_READ 0x9738500 1 0>,
|
|
<DCC_READ 0x973853c 1 0>,
|
|
<DCC_READ 0x9738a04 1 0>,
|
|
<DCC_READ 0x9738a18 1 0>,
|
|
<DCC_READ 0x9738ea8 1 0>,
|
|
<DCC_READ 0x9739044 1 0>,
|
|
<DCC_READ 0x973904c 1 0>,
|
|
<DCC_READ 0x9739054 1 0>,
|
|
<DCC_READ 0x973905c 1 0>,
|
|
<DCC_READ 0x973910c 2 0>,
|
|
<DCC_READ 0x9739204 1 0>,
|
|
<DCC_READ 0x973920c 1 0>,
|
|
<DCC_READ 0x9739238 1 0>,
|
|
<DCC_READ 0x9739240 1 0>,
|
|
<DCC_READ 0x973926c 1 0>,
|
|
<DCC_READ 0x9739394 1 0>,
|
|
<DCC_READ 0x973939c 1 0>,
|
|
<DCC_READ 0x9739704 1 0>,
|
|
<DCC_READ 0x973970c 1 0>,
|
|
<DCC_READ 0x9770868 1 0>,
|
|
<DCC_READ 0x9770870 1 0>,
|
|
<DCC_READ 0x9771004 1 0>,
|
|
<DCC_READ 0x977100c 1 0>,
|
|
<DCC_READ 0x9771014 1 0>,
|
|
<DCC_READ 0x9771204 1 0>,
|
|
<DCC_READ 0x977120c 1 0>,
|
|
<DCC_READ 0x9771214 1 0>,
|
|
<DCC_READ 0x9771504 1 0>,
|
|
<DCC_READ 0x977150c 1 0>,
|
|
<DCC_READ 0x9771514 1 0>,
|
|
<DCC_READ 0x9771604 1 0>,
|
|
<DCC_READ 0x9778100 1 0>,
|
|
<DCC_READ 0x977813c 1 0>,
|
|
<DCC_READ 0x9778500 1 0>,
|
|
<DCC_READ 0x977853c 1 0>,
|
|
<DCC_READ 0x9778a04 1 0>,
|
|
<DCC_READ 0x9778a18 1 0>,
|
|
<DCC_READ 0x9778ea8 1 0>,
|
|
<DCC_READ 0x9779044 1 0>,
|
|
<DCC_READ 0x977904c 1 0>,
|
|
<DCC_READ 0x9779054 1 0>,
|
|
<DCC_READ 0x977905c 1 0>,
|
|
<DCC_READ 0x977910c 2 0>,
|
|
<DCC_READ 0x9779204 1 0>,
|
|
<DCC_READ 0x977920c 1 0>,
|
|
<DCC_READ 0x9779238 1 0>,
|
|
<DCC_READ 0x9779240 1 0>,
|
|
<DCC_READ 0x977926c 1 0>,
|
|
<DCC_READ 0x9779394 1 0>,
|
|
<DCC_READ 0x977939c 1 0>,
|
|
<DCC_READ 0x9779704 1 0>,
|
|
<DCC_READ 0x977970c 1 0>,
|
|
<DCC_READ 0x910d100 3 0>,
|
|
<DCC_READ 0x914d100 3 0>,
|
|
<DCC_READ 0x918d100 4 0>,
|
|
<DCC_READ 0x91a5100 1 0>,
|
|
<DCC_READ 0x91ad100 1 0>;
|
|
};
|
|
|
|
link_list3 {
|
|
qcom,curr-link-list = <7>;
|
|
qcom,data-sink = "sram";
|
|
qcom,link-list = <DCC_READ 0x9050078 1 0>,
|
|
<DCC_READ 0x9050110 8 0>,
|
|
<DCC_READ 0x9080058 2 0>,
|
|
<DCC_READ 0x90800c8 1 0>,
|
|
<DCC_READ 0x90800d4 1 0>,
|
|
<DCC_READ 0x90800e0 1 0>,
|
|
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<DCC_READ 0x977970c 1 0>,
|
|
<DCC_READ 0x910d100 3 0>,
|
|
<DCC_READ 0x914d100 3 0>,
|
|
<DCC_READ 0x918d100 4 0>,
|
|
<DCC_READ 0x91a5100 1 0>,
|
|
<DCC_READ 0x91ad100 1 0>;
|
|
};
|
|
|
|
};
|
|
|
|
qfprom: qfprom@780000 {
|
|
compatible = "qcom,qfprom";
|
|
reg = <0x00784000 0x3000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
read-only;
|
|
ranges;
|
|
|
|
gpu_lm_efuse: gpu_lm_efuse@5c8 {
|
|
reg = <0x5c8 0x4>;
|
|
};
|
|
|
|
gpu_speed_bin: gpu_speed_bin@19b {
|
|
reg = <0x19b 0x1>;
|
|
bits = <5 3>;
|
|
};
|
|
};
|
|
|
|
kryo-erp {
|
|
compatible = "arm,arm64-kryo-cpu-erp";
|
|
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "l1-l2-faultirq",
|
|
"l3-scu-faultirq";
|
|
};
|
|
|
|
msm_gpu: qcom,kgsl-3d0@3d00000 { };
|
|
|
|
qcom,msm-rtb {
|
|
compatible = "qcom,msm-rtb";
|
|
qcom,rtb-size = <0x100000>;
|
|
};
|
|
|
|
};
|
|
|
|
#include "ipcc-test.dtsi"
|
|
#include "kona-usb.dtsi"
|
|
#include "kona-regulators.dtsi"
|
|
#include "kona-pmic-overlay.dtsi"
|
|
#include "kona-thermal.dtsi"
|
|
#include "kona-pinctrl.dtsi"
|
|
#include "msm-arm-smmu-kona.dtsi"
|
|
#include "kona-dma-heaps.dtsi"
|
|
#include "kona-qupv3.dtsi"
|
|
#include "kona-pcie.dtsi"
|
|
#include "kona-smp2p.dtsi"
|
|
#include "msm-rdbg.dtsi"
|
|
#include "kona-thermal.dtsi"
|
|
#include "kona-coresight.dtsi"
|