298 lines
9.8 KiB
Text
298 lines
9.8 KiB
Text
&soc {
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/* GPI Instance */
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gpi_dma0: qcom,gpi-dma@4a00000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x4a00000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0xf6 0x0>;
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qcom,max-num-gpii = <10>;
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interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
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qcom,gpii-mask = <0x1f>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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qcom,gpi-ee-offset = <0x10000>;
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dma-coherent;
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status = "ok";
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};
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/* QUPv3_0 wrapper instance */
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qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x4ac0000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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iommus = <&apps_smmu 0xe3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok";
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qupv3_se0_i2c: i2c@4a80000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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dmas = <&gpi_dma0 0 0 3 64 0>,
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<&gpi_dma0 1 0 3 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se0_spi: spi@4a80000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_spi_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep>;
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dmas = <&gpi_dma0 0 0 1 64 0>,
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<&gpi_dma0 1 0 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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/* 4-wire UART Instance for DIAG */
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qupv3_se0_4uart: qcom,qup_uart@4a80000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x4a80000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "active", "sleep", "shutdown";
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pinctrl-0 = <&qupv3_se0_default_ctsrtsrx>,
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<&qupv3_se0_default_tx>;
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pinctrl-1 = <&qupv3_se0_ctsrx>, <&qupv3_se0_rts>,
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<&qupv3_se0_tx>;
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pinctrl-2 = <&qupv3_se0_ctsrx>, <&qupv3_se0_rts>,
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<&qupv3_se0_tx>;
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pinctrl-3 = <&qupv3_se0_default_ctsrtsrx>,
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<&qupv3_se0_default_tx>;
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status = "disabled";
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};
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qupv3_se1_i2c: i2c@4a84000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a84000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_i2c_active>;
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pinctrl-1 = <&qupv3_se1_i2c_sleep>;
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dmas = <&gpi_dma0 0 1 3 64 0>,
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<&gpi_dma0 1 1 3 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se1_spi: spi@4a84000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a84000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_spi_active>;
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pinctrl-1 = <&qupv3_se1_spi_sleep>;
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dmas = <&gpi_dma0 0 1 1 64 0>,
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<&gpi_dma0 1 1 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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qupv3_se2_i2c: i2c@4a88000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a88000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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dmas = <&gpi_dma0 0 2 3 64 0>,
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<&gpi_dma0 1 2 3 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se2_spi: spi@4a88000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a88000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_spi_active>;
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pinctrl-1 = <&qupv3_se2_spi_sleep>;
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dmas = <&gpi_dma0 0 2 1 64 0>,
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<&gpi_dma0 1 2 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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/* HS UART Instance */
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qupv3_se3_4uart: qcom,qup_uart@4a8c000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x4a8c000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "active", "sleep", "shutdown";
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pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>,
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<&qupv3_se3_default_tx>;
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pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
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<&qupv3_se3_tx>;
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pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
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<&qupv3_se3_tx>;
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pinctrl-3 = <&qupv3_se3_default_ctsrtsrx>,
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<&qupv3_se3_default_tx>;
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qcom,wakeup-byte = <0xFD>;
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status = "disabled";
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};
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/* Debug UART Instance */
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qupv3_se4_2uart: qcom,qup_uart@4a90000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x4a90000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_2uart_active>;
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pinctrl-1 = <&qupv3_se4_2uart_sleep>;
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status = "disabled";
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};
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qupv3_se5_i2c: i2c@4a94000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a94000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_i2c_active>;
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pinctrl-1 = <&qupv3_se5_i2c_sleep>;
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dmas = <&gpi_dma0 0 5 3 64 0>,
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<&gpi_dma0 1 5 3 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se5_spi: spi@4a94000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a94000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_spi_active>;
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pinctrl-1 = <&qupv3_se5_spi_sleep>;
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dmas = <&gpi_dma0 0 5 1 64 0>,
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<&gpi_dma0 1 5 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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};
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};
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