1210 lines
25 KiB
Text
1210 lines
25 KiB
Text
#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,scuba.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/qcom,gcc-scuba.h>
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#include <dt-bindings/clock/qcom,gpucc-scuba.h>
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#include <dt-bindings/clock/qcom,dispcc-scuba.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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/ {
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model = "Qualcomm Technologies, Inc. SCUBA_AUTO";
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compatible = "qcom,sa410m";
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qcom,msm-id = <441 0x10000>, <471 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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reserved_memory: reserved-memory { };
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chosen: chosen {
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bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
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};
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mem-offline {
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compatible = "qcom,mem-offline";
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offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
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<0x1 0xc0000000 0x0 0x80000000>,
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<0x2 0xc0000000 0x1 0x40000000>;
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granule = <512>;
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};
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aliases {
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serial0= &qupv3_se4_2uart ;
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sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/
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};
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firmware: firmware {};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L1_I_1: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_1: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L1_I_2: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_2: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L1_I_3: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_3: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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soc: soc { };
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};
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&reserved_memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_region: hyp_region@45600000 {
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no-map;
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reg = <0x0 0x45600000 0x0 0x700000>;
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};
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xbl_aop_mem: xbl_aop_mem@45d00000 {
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no-map;
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reg = <0x0 0x45d00000 0x0 0x200000>;
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};
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sec_apps_mem: sec_apps_region@45fff000 {
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no-map;
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reg = <0x0 0x45fff000 0x0 0x1000>;
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};
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smem_region: smem@46000000 {
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no-map;
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reg = <0x0 0x46000000 0x0 0x200000>;
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};
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pil_modem_mem: modem_region@4ab00000 {
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no-map;
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reg = <0x0 0x4ab00000 0x0 0x6900000>;
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};
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wlan_msa_mem: wlan_msa_region@51400000 {
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no-map;
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reg = <0x0 0x51400000 0x0 0x100000>;
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};
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pil_adsp_mem: adsp_regions@51500000 {
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no-map;
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reg = <0x0 0x51500000 0x0 0x1400000>;
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};
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pil_ipa_fw_mem: ips_fw_region@52900000 {
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no-map;
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reg = <0x0 0x52900000 0x0 0x10000>;
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};
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pil_ipa_gsi_mem: ipa_gsi_region@52910000 {
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no-map;
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reg = <0x0 0x52910000 0x0 0x5000>;
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};
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pil_reserved_unused_mem: pil_reserved_unused_region@52915000 {
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no-map;
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reg = <0x0 0x52915000 0x0 0xEB000>;
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};
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tz_stat: tz_stat@53200000 {
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no-map;
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reg = <0x0 0x53200000 0x0 0x100000>;
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};
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pimem_vault: pimem_vault@53300000 {
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no-map;
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reg = <0x0 0x53300000 0x0 0x1500000>;
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};
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adsp_mem: adsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x00000000 0 0xffffffff>;
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x800000>;
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};
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dump_mem: mem_dump_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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size = <0 0x800000>;
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};
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user_contig_mem: user_contig_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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qseecom_mem: qseecom_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x700000>;
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};
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qseecom_ta_mem: qseecom_ta_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x400000>;
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};
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memshare_mem: memshare_region {
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compatible = "shared-dma-pool";
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no-map;
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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alignment = <0x0 0x100000>;
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size = <0x0 0x800000>;
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};
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/* global autoconfigured region for contiguous allocations */
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system_cma:linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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&firmware {
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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};
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qcom_smcinvoke {
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compatible = "qcom,smcinvoke";
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@f200000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0xf200000 0x10000>, /* GICD */
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<0xf300000 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <0>;
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};
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rpm_bus: qcom,rpm-smd {
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compatible = "qcom,rpm-smd";
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rpm-channel-name = "rpm_requests";
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interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
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rpm-channel-type = <15>; /* SMD_APPS_RPM */
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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qcom_tzlog: tz-log@c125720 {
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compatible = "qcom,tz-log";
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reg = <0xc125720 0x3000>;
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qcom,hyplog-enabled;
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hyplog-address-offset = <0x410>;
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hyplog-size-offset = <0x414>;
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};
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qcom_qseecom: qseecom@c1700000 {
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compatible = "qcom,qseecom";
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memory-region = <&qseecom_mem>;
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qseecom_mem = <&qseecom_mem>;
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qseecom_ta_mem = <&qseecom_ta_mem>;
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user_contig_mem = <&user_contig_mem>;
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qcom,hlos-num-ce-hw-instances = <1>;
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qcom,hlos-ce-hw-instance = <0>;
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qcom,qsee-ce-hw-instance = <0>;
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qcom,disk-encrypt-pipe-pair = <2>;
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qcom,no-clock-support;
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qcom,appsbl-qseecom-support;
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qcom,commonlib64-loaded-by-uefi;
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qcom,qsee-reentrancy-support = <2>;
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};
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memtimer: timer@f120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xf120000 0x1000>;
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clock-frequency = <19200000>;
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frame@f121000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf121000 0x1000>,
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<0xf122000 0x1000>;
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};
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frame@f123000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf123000 0x1000>;
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status = "disabled";
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};
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frame@f124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf124000 0x1000>;
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status = "disabled";
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};
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frame@f125000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf125000 0x1000>;
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status = "disabled";
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};
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frame@f126000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf126000 0x1000>;
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status = "disabled";
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};
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frame@f127000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf127000 0x1000>;
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status = "disabled";
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};
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frame@f128000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf128000 0x1000>;
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status = "disabled";
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};
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};
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qcom,msm-imem@c125000 {
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compatible = "qcom,msm-imem";
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reg = <0xc125000 0x1000>;
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ranges = <0x0 0xc125000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mem_dump_table@10 {
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compatible = "qcom,msm-imem-mem_dump_table";
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reg = <0x10 0x8>;
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};
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dload_type@1c {
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compatible = "qcom,msm-imem-dload-type";
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reg = <0x1c 0x4>;
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};
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restart_reason@65c {
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compatible = "qcom,msm-imem-restart_reason";
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reg = <0x65c 0x4>;
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};
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boot_stats@6b0 {
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compatible = "qcom,msm-imem-boot_stats";
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reg = <0x6b0 0x20>;
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};
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kaslr_offset@6d0 {
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compatible = "qcom,msm-imem-kaslr_offset";
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reg = <0x6d0 0xc>;
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};
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pil@94c {
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compatible = "qcom,pil-reloc-info";
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reg = <0x94c 0xc8>;
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};
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pil@6dc {
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compatible = "qcom,msm-imem-pil-disable-timeout";
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reg = <0x6dc 0x4>;
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};
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diag_dload@c8 {
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compatible = "qcom,msm-imem-diag-dload";
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reg = <0xc8 0xc8>;
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};
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};
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dload_mode {
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compatible = "qcom,dload-mode";
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};
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wdog: qcom,wdt@f017000 {
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compatible = "qcom,msm-watchdog";
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reg = <0xf017000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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rpm_msg_ram: memory@045f0000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0x45f0000 0x7000>;
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};
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apcs_glb: mailbox@0f111000 {
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compatible = "qcom,scuba-apcs-hmss-global";
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reg = <0xF111000 0x1000>;
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#mbox-cells = <1>;
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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mboxes = <&apcs_glb 0>;
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qcom,rpm_glink_ssr {
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qcom,glink-channels = "glink_ssr";
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// qcom,notify-edges = <&glink_adsp>;
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};
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};
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mem_dump {
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compatible = "qcom,mem-dump";
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memory-region = <&dump_mem>;
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c0_context {
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qcom,dump-size = <0x800>;
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qcom,dump-id = <0x0>;
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};
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c1_context {
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qcom,dump-size = <0x800>;
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qcom,dump-id = <0x1>;
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};
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c2_context {
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qcom,dump-size = <0x800>;
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qcom,dump-id = <0x2>;
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};
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c3_context {
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qcom,dump-size = <0x800>;
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qcom,dump-id = <0x3>;
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};
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l1_icache0 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x60>;
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};
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l1_icache1 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x61>;
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};
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l1_icache2 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x62>;
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};
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l1_icache3 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x63>;
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};
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l1_dcache0 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x80>;
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};
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l1_dcache1 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x81>;
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};
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l1_dcache2 {
|
|
qcom,dump-size = <0x9040>;
|
|
qcom,dump-id = <0x82>;
|
|
};
|
|
|
|
l1_dcache3 {
|
|
qcom,dump-size = <0x9040>;
|
|
qcom,dump-id = <0x83>;
|
|
};
|
|
|
|
l2_tlb0 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x120>;
|
|
};
|
|
|
|
l2_tlb1 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x121>;
|
|
};
|
|
|
|
l2_tlb2 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x122>;
|
|
};
|
|
|
|
l2_tlb3 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x123>;
|
|
};
|
|
|
|
spm_reg {
|
|
qcom,dump-size = <0x400>;
|
|
qcom,dump-id = <0x164>;
|
|
};
|
|
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo-board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <38400000>;
|
|
clock-output-names = "xo_board";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sleep_clk: sleep-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "chip_sleep_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
rpmcc: clock-controller {
|
|
compatible = "qcom,rpmcc-scuba";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gcc: clock-controller@1400000 {
|
|
compatible = "qcom,scuba-gcc", "syscon";
|
|
reg = <0x1400000 0x1f0000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
|
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
|
|
<&sleep_clk>;
|
|
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc: clock-controller@5f00000 {
|
|
compatible = "qcom,scuba-dispcc", "syscon";
|
|
reg = <0x5f00000 0x20000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
|
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
|
|
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
|
|
<&sleep_clk>;
|
|
clock-names = "bi_tcxo", "bi_tcxo_ao",
|
|
"gcc_disp_gpll0_div_clk_src",
|
|
"sleep_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpucc: clock-controller@5990000 {
|
|
compatible = "qcom,scuba-gpucc", "syscon";
|
|
reg = <0x5990000 0x9000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
|
|
clock-names = "bi_tcxo", "gpll0_out_main";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@00340000 {
|
|
compatible = "syscon";
|
|
reg = <0x340000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
smem: qcom,smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_region>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apcs_glb 14>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
|
|
qcom,entry-name = "ipa";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
/* ipa - inbound entry from mss */
|
|
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
|
|
qcom,entry-name = "ipa";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apcs_glb 10>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
adsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
adsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
modem_pas: remoteproc-modem@6080000 {
|
|
compatible = "qcom,scuba_auto-modem-pas";
|
|
reg = <0x6080000 0x100>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
|
clock-names = "xo";
|
|
status = "ok";
|
|
|
|
cx-supply = <&VDD_CX_LEVEL>;
|
|
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
|
reg-names = "vdd_cx";
|
|
|
|
memory-region = <&pil_modem_mem>;
|
|
|
|
/* Inputs from mss */
|
|
interrupts-extended = <&intc 0 307 1>,
|
|
<&modem_smp2p_in 0 0>,
|
|
<&modem_smp2p_in 2 0>,
|
|
<&modem_smp2p_in 1 0>,
|
|
<&modem_smp2p_in 3 0>,
|
|
<&modem_smp2p_in 7 0>;
|
|
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"handover",
|
|
"ready",
|
|
"stop-ack",
|
|
"shutdown-ack";
|
|
|
|
/* Outputs to mss */
|
|
qcom,smem-states = <&modem_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
glink_modem: glink-edge {
|
|
qcom,remote-pid = <1>;
|
|
transport = "smem";
|
|
mboxes = <&apcs_glb 12>;
|
|
mbox-names = "mpss_smem";
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "modem";
|
|
qcom,glink-label = "mpss";
|
|
|
|
qcom,modem_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,low-latency;
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
|
|
remoteproc-lpass@ab00000 {
|
|
compatible = "qcom,scuba_auto-lpass-pas";
|
|
reg = <0xab00000 0x00100>;
|
|
status = "ok";
|
|
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
|
clock-names = "xo";
|
|
qcom,proxy-clock-names = "xo";
|
|
|
|
x-supply = <&VDD_LPI_CX_LEVEL>;
|
|
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
mx-supply = <&VDD_LPI_MX_LEVEL>;
|
|
mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
|
|
|
|
memory-region = <&pil_adsp_mem>;
|
|
|
|
/* Inputs from lpass */
|
|
interrupts-extended = <&intc 0 282 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&adsp_smp2p_in 0 0>,
|
|
<&adsp_smp2p_in 2 0>,
|
|
<&adsp_smp2p_in 1 0>,
|
|
<&adsp_smp2p_in 3 0>;
|
|
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"handover",
|
|
"ready",
|
|
"stop-ack";
|
|
|
|
/* Outputs to lpass */
|
|
qcom,smem-states = <&adsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
glink_adsp: glink-edge {
|
|
qcom,remote-pid = <2>;
|
|
transport = "smem";
|
|
mboxes = <&apcs_glb 8>;
|
|
mbox-names = "adsp_smem";
|
|
interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "adsp";
|
|
qcom,glink-label = "lpass";
|
|
|
|
qcom,adsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,low-latency;
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,apr_tal_rpmsg {
|
|
qcom,glink-channels = "apr_audio_svc";
|
|
qcom,intents = <0x200 20>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,ipa_fws {
|
|
compatible = "qcom,pil-tz-generic";
|
|
qcom,pas-id = <0xf>;
|
|
qcom,firmware-name = "scuba_ipa_fws";
|
|
qcom,pil-force-shutdown;
|
|
memory-region = <&pil_ipa_fw_mem>;
|
|
};
|
|
|
|
qcom-secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
};
|
|
|
|
qcom_scm: qcomscm {
|
|
compatible = "qcom,scm";
|
|
};
|
|
|
|
sdhc_1: sdhci@4744000 {
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
|
|
reg-names = "hc", "cqhci";
|
|
|
|
iommus = <&apps_smmu 0xC0 0x0>;
|
|
qcom,iommu-dma = "bypass";
|
|
|
|
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
|
|
<&gcc GCC_SDCC1_AHB_CLK>,
|
|
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
|
|
clock-names = "core", "iface", "ice_core";
|
|
|
|
qcom,ice-clk-rates = <300000000 100000000>;
|
|
|
|
//interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>,
|
|
// <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>;
|
|
//interconnect-names = "sdhc-ddr","cpu-sdhc";
|
|
//qcom,msm-bus,name = "sdhc1";
|
|
//qcom,msm-bus,num-cases = <9>;
|
|
//qcom,msm-bus,num-paths = <2>;
|
|
//qcom,msm-bus,vectors-KBps =
|
|
/* No vote */
|
|
// <0 0>, <0 0>,
|
|
/* 400 KB/s*/
|
|
// <1046 1600>,
|
|
// <1600 1600>,
|
|
/* 20 MB/s */
|
|
// <20480 80000>,
|
|
// <80000 80000>,
|
|
/* 25 MB/s */
|
|
// <25600 250000>,
|
|
// <50000 133320>,
|
|
/* 50 MB/s */
|
|
// <51200 250000>,
|
|
// <65000 133320>,
|
|
/* 100 MB/s */
|
|
// <102400 250000>,
|
|
// <65000 133320>,
|
|
// /* 200 MB/s */
|
|
// <204800 800000>,
|
|
// <200000 300000>,
|
|
/* 400 MB/s */
|
|
// <204800 800000>,
|
|
// <200000 300000>,
|
|
/* Max. bandwidth */
|
|
// <1338562 4096000>,
|
|
// <1338562 4096000>;
|
|
//qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
|
|
// 100750000 200000000 400000000 4294967295>;
|
|
|
|
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
|
qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>;
|
|
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
mmc-hs400-enhanced-strobe;
|
|
|
|
bus-width = <8>;
|
|
non-removable;
|
|
supports-cqe;
|
|
|
|
no-sd;
|
|
no-sdio;
|
|
max-frequency = <192000000>;
|
|
|
|
//qcom,devfreq,freq-table = <50000000 200000000>;
|
|
//qcom,scaling-lower-bus-speed-mode = "DDR52";
|
|
|
|
status = "disabled";
|
|
|
|
qos0 {
|
|
mask = <0x0f>;
|
|
vote = <43>;
|
|
};
|
|
};
|
|
|
|
mccc_debug: syscon@447d200 {
|
|
compatible = "syscon";
|
|
reg = <0x447d200 0x100>;
|
|
};
|
|
|
|
cpucc_debug: syscon@f11101c {
|
|
compatible = "syscon";
|
|
reg = <0xf11101c 0x4>;
|
|
};
|
|
|
|
debugcc: clock-controller@0 {
|
|
compatible = "qcom,scuba-debugcc";
|
|
qcom,gcc = <&gcc>;
|
|
qcom,dispcc = <&dispcc>;
|
|
qcom,gpucc = <&gpucc>;
|
|
qcom,mccc = <&mccc_debug>;
|
|
qcom,cpucc = <&cpucc_debug>;
|
|
clock-names = "xo_clk_src";
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
cpufreq_hw: qcom,cpufreq-hw {
|
|
compatible = "qcom,cpufreq-hw";
|
|
reg = <0xf521000 0x1400>;
|
|
reg-names = "freq-domain0";
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
qcom,no-accumulative-counter;
|
|
qcom,max-lut-entries = <12>;
|
|
#freq-domain-cells = <1>;
|
|
};
|
|
|
|
spmi_bus: qcom,spmi@1c40000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x1c40000 0x1100>,
|
|
<0x1e00000 0x2000000>,
|
|
<0x3e00000 0x100000>,
|
|
<0x3f00000 0xa0000>,
|
|
<0x1c0a000 0x26000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
cell-index = <0>;
|
|
};
|
|
|
|
thermal_zones: thermal-zones { };
|
|
|
|
clk_virt: interconnect@0 {
|
|
compatible = "qcom,scuba-clk_virt";
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_QUP_CLK>,
|
|
<&rpmcc RPM_SMD_QUP_A_CLK>;
|
|
};
|
|
|
|
system_noc: interconnect0@1880000 {
|
|
reg = <0x1880000 0x5e080>;
|
|
compatible = "qcom,scuba-sys_noc";
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
|
|
<&rpmcc RPM_SMD_SNOC_A_CLK>;
|
|
};
|
|
|
|
mmnrt_virt: interconnect1@1880000 {
|
|
reg = <0x1880000 0x5e080>;
|
|
compatible = "qcom,scuba-mmnrt_virt";
|
|
qcom,util-factor = <142>;
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_MMNRT_CLK>,
|
|
<&rpmcc RPM_SMD_MMNRT_A_CLK>;
|
|
};
|
|
|
|
mmrt_virt: interconnect2@1880000 {
|
|
reg = <0x1880000 0x5e080>;
|
|
compatible = "qcom,scuba-mmrt_virt";
|
|
qcom,util-factor = <139>;
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_MMRT_CLK>,
|
|
<&rpmcc RPM_SMD_MMRT_A_CLK>;
|
|
};
|
|
|
|
config_noc: interconnect@1900000 {
|
|
reg = <0x01900000 0x9200>;
|
|
compatible = "qcom,scuba-config_noc";
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
|
|
<&rpmcc RPM_SMD_CNOC_A_CLK>;
|
|
};
|
|
|
|
bimc: interconnect@4480000 {
|
|
reg = <0x4480000 0x80000>;
|
|
compatible = "qcom,scuba-bimc";
|
|
qcom,util-factor = <153>;
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
|
|
<&rpmcc RPM_SMD_BIMC_A_CLK>;
|
|
};
|
|
|
|
tlmm: pinctrl@500000 {
|
|
compatible = "qcom,scuba_auto-pinctrl";
|
|
reg = <0x500000 0x300000>;
|
|
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
//wakeup-parent = <&wakegic>;
|
|
};
|
|
|
|
qcom-secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
};
|
|
|
|
qcom_scm: qcomscm {
|
|
compatible = "qcom,scm";
|
|
};
|
|
|
|
qcom,rmtfs_sharedmem@0 {
|
|
compatible = "qcom,sharedmem-uio";
|
|
reg = <0x0 0x280000>;
|
|
reg-names = "rmtfs";
|
|
qcom,client-id = <0x00000001>;
|
|
qcom,vm-nav-path;
|
|
};
|
|
|
|
qcom,memshare {
|
|
compatible = "qcom,memshare";
|
|
|
|
qcom,client_1 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x0>;
|
|
qcom,client-id = <0>;
|
|
qcom,allocate-boot-time;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_2 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x0>;
|
|
qcom,client-id = <2>;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_3 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x500000>;
|
|
memory-region = <&memshare_mem>;
|
|
qcom,client-id = <1>;
|
|
qcom,allocate-on-request;
|
|
label = "modem";
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "scuba_auto-pmic.dtsi"
|
|
#include "pm2250-rpm-regulator.dtsi"
|
|
#include "scuba-regulator.dtsi"
|
|
#include "monaco-gdsc.dtsi"
|
|
#include "scuba_auto-pinctrl.dtsi"
|
|
|
|
&gcc_camss_top_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_usb30_prim_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_vcodec0_gdsc {
|
|
reg = <0x1458098 0x4>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_venus_gdsc {
|
|
reg = <0x145807c 0x4>;
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {
|
|
qcom,gds-timeout = <500>;
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {
|
|
qcom,gds-timeout = <500>;
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&mdss_core_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_gx_sw_reset {
|
|
reg = <0x5991008 0x4>;
|
|
};
|
|
|
|
&gpu_cx_hw_ctrl {
|
|
reg = <0x5991540 0x4>;
|
|
};
|
|
|
|
&gpu_gx_domain_addr {
|
|
reg = <0x5991508 0x4>;
|
|
};
|
|
|
|
&gpu_cx_gdsc {
|
|
reg = <0x599106c 0x4>;
|
|
/delete-property/ qcom,gds-timeout;
|
|
/delete-property/ qcom,clk-dis-wait-val;
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_gx_gdsc {
|
|
reg = <0x599100c 0x4>;
|
|
status = "ok";
|
|
};
|
|
|
|
#include "msm-arm-smmu-scuba_auto.dtsi"
|
|
#include "scuba_auto-qupv3.dtsi"
|
|
#include "scuba_auto-dma-heap.dtsi"
|
|
|
|
&sdhc_1 {
|
|
vdd-supply = <&L20A>;
|
|
qcom,vdd-voltage-level = <2856000 2856000>;
|
|
qcom,vdd-current-level = <0 570000>;
|
|
|
|
vdd-io-supply = <&L14A>;
|
|
qcom,vdd-io-always-on;
|
|
qcom,vdd-io-lpm-sup;
|
|
qcom,vdd-io-voltage-level = <1800000 1800000>;
|
|
qcom,vdd-io-current-level = <0 325000>;
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&sdc1_on>;
|
|
pinctrl-1 = <&sdc1_off>;
|
|
status = "ok";
|
|
};
|
|
|
|
&qupv3_se4_2uart {
|
|
status = "ok";
|
|
};
|